Circuit for write field disturbance cancellation in an MRAM...

Details Circuit for write field disturbance cancellation in an MRAM... Circuit for write field disturbance cancellation in an MRAM...

2005-02-22

2005-02-22

Mai, Son (Department: 2818)

Static information storage and retrieval

Systems using particular element

Magnetoresistive

C365S171000, C365S173000

Reexamination Certificate

active

06859388

ABSTRACT:
A circuit and method for counteracting stray magnetic fields generated by write currents in an MRAM memory reuses the write current in adjoining write columns via a current redistribution bus at a first end of the write lines. A first switch connected to a second end of each write line controls the write current in the write line. If the first switch is not conductive, a second switch connects the second end of the write line to a reference voltage terminal. For write lines located at sub-array edges, a predetermined amount of spacing may be used to avoid magnetic field disturbance in an adjacent sub-array. The number of spaces required can be minimized by specific activation of write line switches.

REFERENCES:
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patent: 1 202 284 (2002-05-01), None
U.S. patent application 10/656,676.

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