Circuit for varying read timing

Details Circuit for varying read timing Circuit for varying read timing

1995-04-27

1997-03-04

Hudspeth, David R.

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

322166, 322252, H03K 1728

Patent

active

056083432

ABSTRACT:
A circuit changes the timing for reading data by varying bias potential applied to a clock signal used to read the data. The circuit has a comparator for comparing an external clock signal with a reference voltage that provides a logic decision level and generating an internal clock signal, and a logic circuit for fetching input data in synchronization with the internal clock signal. The comparator has a bias changer. The bias changer applies DC bias potential to the external clock signal to the comparator, to change the phase of the internal clock signal.

REFERENCES:
patent: 3764920 (1973-10-01), Galcik et al.
patent: 4585952 (1986-04-01), Yamamoto
patent: 4588905 (1986-05-01), Kojima
patent: 4746819 (1988-05-01), Kashiwagi
patent: 4929849 (1990-05-01), Paul

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