Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
1998-01-27
2001-02-13
Yoo, Do Hyun (Department: 2759)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S138000, C711S158000, C710S053000
Reexamination Certificate
active
06189075
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to memory circuits, and, more particularly, to a circuit for the control of memory in a multiple-user environment with access request and access priority. This type of circuit is used in multiprocessor applications each possessing a local working memory. The applications relating to image processing often have recourse to this type of system, with the image processing operations being generally done by blocks that may be processed separately.
BACKGROUND OF THE INVENTION
In multiprocessor environments, it is possible to have a memory that is directly accessible by all the processors. However, the arbitration of access is relatively difficult to manage when a large number of processors are used. One approach currently being developed includes the association, with each processor or group of processors, of a small-sized memory (of some kilobytes) that is used as a local working memory. The local working memory contains a copy of a part of the total memory of the system. Furthermore, so that the processors may make the most efficient use of their computation capacities, memory management circuits are used to which the processors address simple requests.
The requests are used to simplify the wiring of the multiprocessor systems. One wire may be enough if the request is only a request for the exchange of information elements between the central memory and the local memory. The request for the exchange of information is managed entirely by a memory management circuit which, as a function of parameters corresponding to the processor that performs a request, will determine the direction of the transfer to be made, and the size of the block to be transferred, its position in the central memory and possible authorization of access in write and/or read mode. The memory management circuit and the processors then exchange the data elements in a synchronized manner, significantly reducing the number of wires to manage the exchange.
In a system of this kind, when one request is being processed, no other request can be taken into account before the end of the request. A priority processor may, however, be authorized to interrupt the request in progress for priority needs. In the event of interruption of the request, there occurs a desynchronization of the user devices with respect to the data exchange. The desynchronization makes the exchanged data elements erroneous and requires the exchange to be redone. Now, to carry a new exchange, it is necessary to make a new request which may go through after other requests.
In such a system, the local memories are generally small and very fast, and a central memory is generally very large and fairly slow. Since the use of elementary requests makes it necessary to carry out transfers of synchronized data elements, it causes a stopping of the user devices during the exchange of data elements with the central memory. Furthermore, the data transfer must be done at the speed of the slowest memory. Each user device is, therefore, slowed down by the central memory.
SUMMARY OF THE INVENTION
It is an object of the invention to propose an approach that reduces the possibilities of desynchronization of the transfer of data for the user devices. Another aim of the invention is to make the user devices function at an optimum speed. To do so, in the invention, a first-in/first-out (FIFO) type of buffer circuit is used. One improvement includes totally eliminating the possibility of desynchronization by permitting transfers only if the FIFO buffer memory is full enough or empty enough to perform the transfer without any risk of an interruption of the transfer.
The present invention is directed to an information processing system. The system preferably comprises:
at least two user devices each having one local memory, the local memory being used as a working memory for each of the user devices;
at least one priority access processor;
a central memory whose contents can be used by one of the at least two user devices mentioned above as well as by the at least one processor mentioned above;
a circuit for the management of the central memory that receives requests from user devices and, as a function of the request and of internal information, gives signals to drive the memory and the data exchanges between the memory and the user devices;
a FIFO type buffer memory connected firstly between the management circuit and the central memory and secondly between the user devices and the central memory; and
means for substituting that enables the processor to replace the buffer memory to directly drive the central memory.
Another aspect of the invention is directed to a method for the management of a central memory shared between at least two user devices each having available one local memory by means of a request management circuit to manage the data exchanges between the local memories and the central memory and at least one priority access processor. The method preferably includes steps such that:
the requests sent by the user devices are requests for data exchange that are interpreted by the request management circuit to produce control signals to drive the memory during an exchange of data between the memory and one of the user devices;
the control signals are stored in a FIFO type buffer memory that regulates the bit rate of the control signals between the request management circuit and the memory; and
the processor replaces the buffer memory in order to drive the central memory.
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Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Galanthay Theodore E.
Moazzami Nasser
SGS-Thomson Microelectronics S.A.
Yoo Do Hyun
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