Circuit for the detection of changes of address

Details Circuit for the detection of changes of address Circuit for the detection of changes of address

1998-01-27

2000-08-15

Phan, Trong

Static information storage and retrieval

Read/write circuit

Including signal comparison

365195, G11C 700

Patent

active

061046442

ABSTRACT:
A memory is provided with an addressing circuit comprising an address bus to convey address signals, biasing and selector switch circuits connected to the address bus for the selecting and biasing of lines of the memory and write circuits for the writing of data in cells of the memory. The memory comprises an enabling circuit to enable an operation of writing in memory. This enabling circuit comprises a circuit to memorize a designated address or to write data elements, a comparison circuit to compare a current address available on the address bus with the designated address and a blocking circuit to prevent the writing when the comparison reveals a difference of address.

REFERENCES:
patent: 5036460 (1991-07-01), Takahira et al.
patent: 5682344 (1997-10-01), Seyyedy
French Search Report from French Patent application 97 01232, filed Feb. 4, 1997.
Patent Abstracts of Japan, vol. 016, No. 068 (P-1314), Feb. 19, 1992 & JP-A-03 260993 (NEC Corp.).

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