Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
2001-08-10
2003-02-25
Chang, Daniel (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S062000, C327S039000, C327S323000
Reexamination Certificate
active
06525568
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to digital signal demodulation and detection circuits, especially digital radio signal reception and processing circuits.
The signals modulated by digital information are transmitted by physical circuits that deform these signal, in such a way that the signals have to be processed on arrival in order to retrieve the digital information that they contain. This processing is done by threshold demodulation circuits that convert the variations in analog level of the received signal into binary information (high-level or low-level binary information). This is the case even if the signals have undergone waveform degradation.
Typically, an antenna and amplitude-modulated or frequency-modulated radio signal received from an antenna is demodulated by an amplitude or frequency demodulator, which gives a low-frequency analog signal with a waveform that is rectangular in theory but highly degraded in practice. This signal is applied to a threshold comparator which decides whether the analog signal level received at a given point in time has to be considered as having a high or a low logic level. The comparator therefore carries out a conversion function to convert an analog signal into a logic signal, or again a logic decision-making function for taking a logic decision on the basis of an analog signal.
The threshold of the comparator cannot be fixed in practice because it depends far too much on parameters that may vary (with variable voltage levels, imprecise locking of the demodulators etc).
This is why it is usually preferred to use a comparison threshold that is the mean level of the analog signal. Indeed, the signal is modulated in a binary manner and therefore oscillates permanently as a function of the information that it conveys between its high level and its low level. Its mean level is therefore roughly midway between its high level and its low level.
It is therefore habitual to apply the following signals to the input of the comparator: firstly the analog signal representing the binary information to be detected and, secondly, a signal representing a threshold, this signal being formed by a mean value of the analog signal. Depending on whether the signal is above or below its mean value, the comparator will switch over in one direction of the other, thus converting the degraded waveform signal into a rectangular signal representing the binary information conveyed.
The mean value may be established by means of the simple lowpass filter that receives the analog signal and integrates it over a sufficient period of time.
The higher the time constant of the filter, the more efficient will be the measurement of the mean value, provided however that there is no overall change in the reception level of the signal. However, a high time constant implies a high acquisition time at the start. This may be incompatible with the many systems which are normally on standby and have to start as quickly as possible when an exit from the standby state is requested. Errors in the detection of binary information should not occur during the starting phase because of the time taken to build up a stable mean value. Furthermore, if the mean value of the reception level changes, for example in an application of reception in a mobile device, the system must be capable of adapting to the new mean value without delaying far too much, otherwise there will be loss of information.
A short time constant resolves this problem but if it is too short, it will fluctuate far too quickly and make the system far too sensitive to the noise present in the signal.
It is therefore necessary to have an intermediate time constant that is neither too great nor too small, corresponding for example to about 10 data bits.
However the mean value set up by a lowpass filter is a mean value that is delayed with respect to the reality of the arrival of the analog signal. In other words, the mean value provided at a given instant represents the mean value that the signal had a certain time before this instant. And the higher the time constant of the filter, the greater is the delay. The result of thereof is that, at a given point in time, the threshold comparator compares the signal not with its mean value but with a mean value that it had previously. This may falsify the information detected in applications where the mean value is not stable.
The present invention proposes to reduce this defect by delaying the analog signal by a quantity corresponding to the delay introduced by the filter that sets up the mean value, before applying this delayed signal to the input of the comparator which furthermore receives this mean value as a comparison threshold value
SUMMARY OF THE INVENTION
An object of the invention therefore is a circuit for the conversion of analog signals into logic values, comprising an analog signal input, a mean value filter receiving the signal present at the analog signal input to set up a mean value of this signal, and a threshold comparator having a first input and a second input, and receiving the mean value as a threshold value at the second input, wherein a phase-shifter circuit is interposed between the signal input and the first input of the comparator.
The phase shift introduced by the phase-shifter circuit is preferably such that the analog signal is delayed by a value roughly equal to the delay introduced by the mean value filter before it is applied to the input of the comparator.
The invention therefore provides a better guarantee that the analog signal will be compared with its true mean value and not with the previous mean value.
Preferably, the phase-shifter circuit is a circuit having at least one resistor with a value R connected to a capacitor with a value C. and having a transfer function H equal to (1−RCp)/(1+RCp) where p is the Laplace variable. This type of transfer function corresponds to a phase shift identical to the one introduced by a simple lowpass RC filter. The association between this type of filter and a simple RC circuit therefore optimizes the desired compensation for delay in the present invention.
Furthermore, according to a particularly valuable characteristic of the invention, it has been noted that it is even possible to use the resistor R and capacitor C of the phase-shifter with the transfer function (1−RCp)/(1+RCp) as a mean value filter so that there is no need for two distinct RC assemblies. In particular, it may be planned that the analog signal to be converted into a logic value is applied to the input of the phase-shifter comprising a series RC assembly and that the second input of the comparator (the input to representing the mean value of the analog signal) is connected to the junction point of the resistor R and the capacitor C
In a first embodiment, the phase-shifter comprises an operational amplifier with a non-inverter input connected to the junction point of the resistor and the capacitor and an inverter input, with a second resistor between the signal input and the inverter input and a third resistor between the output of the amplifier and the inverter input.
In a second embodiment designed to prevent the use of a high-gain operational amplifier (which may raise problems of stability in a closed loop and therefore call for compensation capacitors), two amplifiers are used, one having negative unit gain and the other having a positive gain of 2, with an adder receiving the output of the two amplifiers. The input of the first amplifier is connected to the analog signal input. The input of the second amplifier is connected to the junction point of the resistor and the capacitor. The output of the adder gives the delayed analog signal to be applied to the comparator. The transfer function of the phase-shifter is the same as it is with a single operational amplifier.
REFERENCES:
patent: 4385328 (1983-05-01), Tanaka
patent: 4634983 (1987-01-01), Schemmel et al.
patent: 5459311 (1995-10-01), Brosnan
patent: 5706221 (1998-01-01), Paulsen
patent: 5909143 (1999-06-01), Weber
patent: 32 03 559 (1983
Ayraud Michel
Ravatin Jean
Atmel Grenoble S.A.
Chang Daniel
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