Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2007-06-29
2009-08-11
Phung, Anh (Department: 2824)
Static information storage and retrieval
Read/write circuit
Testing
C365S230060
Reexamination Certificate
active
07573764
ABSTRACT:
A circuit for testing word lines of a semiconductor memory device, is provided which includes a first test signal generator configured to generate first test signals in response to test mode signals, a second test signal generator configured to generate a second test signal in response to the test mode signals and a word line test signal, a first address predecoder configured to output first address information signals having first address information in response to the second test signal and a first address signal, and a second address predecoder configured to output second address information signals having second address information in response to the first test signals and second address signals.
REFERENCES:
patent: 5596537 (1997-01-01), Sukegawa et al.
patent: 5901096 (1999-05-01), Inokuchi et al.
patent: 6115306 (2000-09-01), Shore et al.
patent: 6392940 (2002-05-01), Endo et al.
patent: 6438718 (2002-08-01), Cline
patent: 6657915 (2003-12-01), Seo et al.
patent: 10-1998-034259 (1998-08-01), None
patent: 10-0200692 (1999-03-01), None
patent: 10-0223674 (1999-07-01), None
Cooper & Dunham LLP
Hynix / Semiconductor Inc.
Phung Anh
White John P.
LandOfFree
Circuit for testing word line of semiconductor memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Circuit for testing word line of semiconductor memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit for testing word line of semiconductor memory device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4060261