Circuit for testing power-on-reset circuitry

Details Circuit for testing power-on-reset circuitry Circuit for testing power-on-reset circuitry

1993-10-26

1995-09-12

Voeltz, Emanuel T.

Excavating

371 225, 364492, 327198, 395750, H04B 1700

Patent

active

054504171

ABSTRACT:
The power-on-reset test circuit of this invention includes two imbalanced latches to detect the occurrence of a transient power-on-reset signal. The occurrence of a transient power-on-reset signal is latched for later verification during circuit testing. Both latches are designed to default to a low voltage output (Vss) on initial power-up. One of the latches is set by the power-on-reset signal to a high-voltage output (Vcc) state. The other latch is set by a reference-potential input to a low-voltage output state. If the set latch has a high-voltage output and the other latch has a low-voltage output, then the power-on-reset circuitry is functioning properly.

REFERENCES:
patent: 4512019 (1985-04-01), Bodig et al.
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patent: 4591745 (1986-05-01), Shen
patent: 4812677 (1989-03-01), Perry
patent: 4841233 (1989-06-01), Yoshida
patent: 4874965 (1989-10-01), Campardo et al.
patent: 5245577 (1993-09-01), Duesman et al.
patent: 5349586 (1994-09-01), Katsuta
patent: 5369310 (1994-11-01), Badyal et al.
patent: 5376835 (1994-12-01), Van Buskirk et al.

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