Circuit for synchronizing refresh cycles in self-refreshing dram

Details Circuit for synchronizing refresh cycles in self-refreshing dram Circuit for synchronizing refresh cycles in self-refreshing dram

1991-04-15

1993-07-20

Mottola, Steven

Static information storage and retrieval

Read/write circuit

Data refresh

365228, 365233, G11C 700

Patent

active

052299708

ABSTRACT:
The invention is a circuit synchronizing the refresh cycles of a bank of self-refreshing DRAMs. The refresh cycles are synchronized through a bidirectional control path from each self-refreshing DRAM to its respective external refresh pin. An arbitration circuit determines the self-refreshing DRAM having a fastest timing sequence, maintains that timing sequence and shuts down all timing circuits having slower timing sequences. The arbitration circuit of each self-refreshing DRAM provides a refresh signal to each respective refresh circuit.

REFERENCES:
patent: 3859640 (1975-01-01), Eberlein et al.
patent: 4172282 (1979-10-01), Aichelmann, Jr.
patent: 4238842 (1980-12-01), Aichelmann, Jr.
patent: 4406013 (1983-09-01), Reese et al.
patent: 4468759 (1984-08-01), Kung et al.
patent: 4706221 (1987-11-01), Satoh et al.
patent: 4792891 (1988-12-01), Baba
patent: 4807289 (1989-02-01), Nakajima
patent: 4827453 (1989-05-01), Sawada et al.
patent: 4881205 (1989-11-01), Aihara
patent: 4961167 (1990-10-01), Kumanoya et al.

Affiliated with

Also associated with

Rating

Circuit for synchronizing refresh cycles in self-refreshing dram does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Circuit for synchronizing refresh cycles in self-refreshing dram, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit for synchronizing refresh cycles in self-refreshing dram will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1766232