Circuit for synchronizing frequencies of clock signals

Details Circuit for synchronizing frequencies of clock signals Circuit for synchronizing frequencies of clock signals

2001-06-29

2002-07-23

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S115000, C327S116000

Reexamination Certificate

active

06424193

ABSTRACT:

This application relies for priority upon Korean Patent Application No. 2000-45686, filed on Aug. 7, 2000, the contents of which are herein incorporated by reference in their entirety.
FIELD OF THE INVENTION
The present invention relates to a circuit for synchronizing frequencies of two clock signals, and more particularly to a phase-locked loop (PLL) circuit synchronizing an input clock signal having a first frequency with a reference clock signal having a second frequency.
BACKGROUND OF THE INVENTION
With the rapid advances in CMOS process technology, computers with clock frequencies of more 100 MHz are widely used. Even though clock skew has not been an important issue in conventional low-speed synchronization systems, the reduction of the clock skew has become a primary requirement as system clock speed is being increased.
Many clock de-skews or clock synchronization methods have been developed to reduce the clock skew or to avoid system malfunction. Some of these methods are disclosed in “A Dynamic Clock Synchronization Technique for Large Systems” (D. E. Brueske and S. H. K. Embabi, IEEE Trans. On Components, Packaging, and Manufacturing Technology, Part B, vol. 17, no.3 pp. 350-361) and “Low-power Clock Deskew Buffer for High-speed Digital Circuits” (S. I. Liu, IEEE j. Solid-State Circuits, vol. 34, no. 4, pp. 554-558, April 1999), etc. These efforts were, however, focused on the synchronization or de-skew between the same frequencies.
Therefore, there exists a need for systems and methods that can synchronize clock signals of different frequencies.
SUMMARY OF THE INVENTION
The object of the present invention is to provide a circuit and method for synchronizing an input clock signal having a first frequency with a reference clock signal having a second frequency.
According to one aspect of the present invention, the PLL circuit includes a first phase comparator circuit for comparing phases of a first (input) clock signal having a first frequency and a feedback signal and for generating a control voltage corresponding to a phase difference between the first clock signal and the feedback signal. A second phase comparator circuit compares phases of a second (reference) clock signal having a second frequency and an output clock signal and for generating a differential signal indicative of a phase difference between the reference clock signal and an output clock signal. A counter counts data in response to the differential signal of the second phase comparator circuit. The PLL circuit further includes a decoder for generating N bit switching control signals by decoding the counting data from the counter. A voltage-controlled delay line (VCDL) generates a feedback signal in response to the first clock signal after the input clock signal is delayed while the control voltage is applied to the VCDL. The VCDL includes N delay stages which are connected in series corresponding to each bit of the switching control signals and generates the output clock signal in response to a signal from the one of delay stages corresponding to the third switching control signals.
According to another aspect of the present invention, a method is provided for a PLL circuit to allow synchronizing a first (input clock) signal having a first frequency with a second (reference) clock signal having a second frequency. In accordance with the method. A feedback signal which is delayed with respect to the input clock signal by one cycle is generated by delaying the input clock signal. The phases of the input clock signal and the reference clock signal are compared. A differential signal corresponding to a phase difference when the phases of the input clock signal and the reference clock signal are not identical with each other is generated. Data is counted up or down in response to the differential signal. Control signals from the counting data are decoded, and an output clock signal is provided by delaying the input clock signal while the control signals are activated. The method is carried out repeatedly until the phases of the input clock signal and the reference clock signal are identical to each other.
In a preferred embodiment of the present invention, generating the feedback signal includes receiving the input clock signal, comparing phases of the input clock signal and the feedback signal, generating a differential signal when the phases of the input clock signal and the feedback signal are not identical with each other, generating a control voltage corresponding to the differential signal, and generating the feedback signal by delaying the input clock signal while the control voltage is applied to the VCDL. The steps are repeated until the phases of the input clock signal and the feedback signal are identical to each other.


REFERENCES:
patent: 4868514 (1989-09-01), Azevedo et al.
patent: 5088080 (1992-02-01), Ishibashi et al.
patent: 6049238 (2000-04-01), Shimizu et al.

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