Circuit for synchronizing data transfers between two devices ope

Details Circuit for synchronizing data transfers between two devices ope Circuit for synchronizing data transfers between two devices ope

1993-05-25

1998-06-02

Black, Thomas G.

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

395559, G06F 506

Patent

active

057617350

ABSTRACT:
A circuit arrangement synchronizes data transfers between a first device and a second device operating at different data rates. The circuit arrangement is comprised of a plurality of registers for storing data received from a device with the higher data rate. A scan logic circuit counts strobe pulses provided by the device with the higher data rate when data is available on its output bus. Selected counts from the scan logic circuit cause data on the output bus to be sequentially transferred into the plurality of registers. Strobe latch logic keeps track of the loading sequence and, in response thereto, select logic and gate arrangement causes the content of a selected register to be transferred to an output register at each clock signal of the slower device.

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