Circuit for storing information

Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C711S150000, C711S156000, C711S163000, C710S240000

Reexamination Certificate

active

06349371

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a circuit for storing information about modules. In particular, but not exclusively, the circuit stores information on modules connected to an interconnect such as a bus in an integrated circuit.
BACKGROUND TO THE PRESENT INVENTION
Integrated circuits are often provided with debug circuitry which allows the integrated circuit to be debugged. The integrated circuit usually comprises a bus and a plurality of modules connected to the bus which put packets onto the bus. The debug circuitry is one of these modules. The modules also usually include a CPU. In order to operate, the debug circuitry is arranged to receive information from an external tool, put that information onto the bus and to check the response to that information or to output the response to the external tool. The debug circuitry can also carry out internal checks within the integrated circuit.
However, these known circuits have a problem. If the external circuitry identifies that there is a problem with a module, it is difficult to identify what has caused the problem in that module. This is because the module issuing the information causing the difficulty will continue to put information onto the bus. This means that the information in the module may have significantly changed by the time that the module is looked at. This makes it difficult to ascertain why the module in question has caused the problem.
SUMMARY OF THE INVENTION
It is an aim of embodiments of the present invention to address the difficulties of the known arrangements.
According to one aspect of the present invention, there is provided in a system comprising an interconnect and a plurality of modules connected to the interconnect, a circuit for controlling which of said modules is able to put information onto said interconnect, said circuit comprising a store which stores status information for each module, said status information defining if the respective module is permitted to put information on said interconnect.
According to a second aspect of the present invention, there is provided a circuit comprising an interconnect; one or more modules connected to the interconnect; and circuitry for monitoring information put onto the interconnect by one or more modules, said circuitry comprising circuitry for determining if the information on the interconnect matches one or more conditions; and a store storing status information for each module, said status information defining for each module if the module is permitted to put information onto the interconnect, whereby a module is prevented from putting further information onto said interconnect if it is determined that information on the interconnect matches said one or more conditions.
According to a third aspect of the present invention, there is provided a circuit comprising an interconnect; one or more modules connected to the interconnect to put information onto the interconnect; an arbiter for determining which module is permitted to put information onto the interconnect; and a store comprising information for each module which defines if the module is permitted to put information onto said interconnect, said arbiter being connected to said store, wherein said arbiter only allows modules which have status information indicating that the module is permitted to put information onto the interconnect to win access to the interconnect.


REFERENCES:
patent: 4571672 (1986-02-01), Hatada et al.
patent: 4814981 (1989-03-01), Rubinfeld
patent: 5251311 (1993-10-01), Kasai
patent: 5386565 (1995-01-01), Tanaka et al.
patent: 5416910 (1995-05-01), Moyer et al.
patent: 5423050 (1995-06-01), Taylor et al.
patent: 5434804 (1995-07-01), Bock et al.
patent: 5440705 (1995-08-01), Wang et al.
patent: 5448576 (1995-09-01), Russell
patent: 5452432 (1995-09-01), Macachor
patent: 5455936 (1995-10-01), Maemura
patent: 5479652 (1995-12-01), Dreyer et al.
patent: 5483518 (1996-01-01), Whetsel
patent: 5488688 (1996-01-01), Gonzales et al.
patent: 5530965 (1996-06-01), Kawasaki et al.
patent: 5570375 (1996-10-01), Tsai et al.
patent: 5590354 (1996-12-01), Klapproth et al.
patent: 5596734 (1997-01-01), Ferra
patent: 5598551 (1997-01-01), Barajas et al.
patent: 5608881 (1997-03-01), Masumura et al.
patent: 5613153 (1997-03-01), Arimilli et al.
patent: 5619726 (1997-04-01), Seconi et al.
patent: 5627842 (1997-05-01), Brown et al.
patent: 5657273 (1997-08-01), Ayukawa et al.
patent: 5666488 (1997-09-01), Joh
patent: 5682545 (1997-10-01), Kawasaki et al.
patent: 5704034 (1997-12-01), Circello
patent: 5708773 (1998-01-01), Jeppesen, III et al.
patent: 5724549 (1998-03-01), Selgas et al.
patent: 5737516 (1998-04-01), Circello et al.
patent: 5751621 (1998-05-01), Arakawa
patent: 5768152 (1998-06-01), Battaline et al.
patent: 5771240 (1998-06-01), Tobin et al.
patent: 5774701 (1998-06-01), Matsui et al.
patent: 5778237 (1998-07-01), Yamamoto et al.
patent: 5781558 (1998-07-01), Inglis et al.
patent: 5796978 (1998-08-01), Yoshioka et al.
patent: 5828825 (1998-10-01), Eskandari et al.
patent: 5832248 (1998-11-01), Kishi et al.
patent: 5835963 (1998-11-01), Yoshioka et al.
patent: 5848247 (1998-12-01), Matsui et al.
patent: 5860127 (1999-01-01), Shimazaki et al.
patent: 5862387 (1999-01-01), Songer et al.
patent: 5867726 (1999-02-01), Ohsuga et al.
patent: 5884092 (1999-03-01), Kiuchi et al.
patent: 5894562 (1999-04-01), Moyer
patent: 5896550 (1999-04-01), Wehunt et al.
patent: 5918045 (1999-06-01), Nishii et al.
patent: 5930523 (1999-07-01), Kawasaki et al.
patent: 5930833 (1999-07-01), Yoshioka et al.
patent: 5944841 (1999-08-01), Christie
patent: 5950012 (1999-09-01), Shiell et al.
patent: 5953538 (1999-09-01), Duncan et al.
patent: 5956477 (1999-09-01), Ranson et al.
patent: 5978874 (1999-11-01), Singhal et al.
patent: 5978902 (1999-11-01), Mann
patent: 5983017 (1999-11-01), Kemp et al.
patent: 5983379 (1999-11-01), Warren
patent: 6073199 (2000-06-01), Cohen et al.
patent: 0165600 (1991-11-01), None
patent: 0720092 (1993-07-01), None
patent: 0636976 (1995-02-01), None
patent: 0636976 (1995-02-01), None
patent: 0652516 (1995-05-01), None
patent: 0702239 (1996-03-01), None
patent: 0933926 (1999-08-01), None
patent: 0945805 (1999-09-01), None
patent: 0959411 (1999-11-01), None
patent: PCT/JP96/02819 (1996-09-01), None
patent: 8320796 (1996-12-01), None
patent: 8329687 (1996-12-01), None
patent: 9212358 (1997-08-01), None
patent: 9311786 (1997-12-01), None
patent: 10106269 (1998-04-01), None
patent: 10124484 (1998-05-01), None
patent: 10177520 (1998-06-01), None
Richard York; Real Time Debug for System-on-Chip Devices; Jun. 1999; pp. 1-6.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Circuit for storing information does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Circuit for storing information, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit for storing information will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2972267

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.