Circuit for SRAM test mode isolated bitline modulation

Details Circuit for SRAM test mode isolated bitline modulation Circuit for SRAM test mode isolated bitline modulation

1995-04-12

1996-10-22

Zarabian, A.

Static information storage and retrieval

Read/write circuit

Testing

365154, G11C 700

Patent

active

055684351

ABSTRACT:
A circuit and method provide isolated modulation of SRAM bitline voltage levels for improved voltage bump retention testing of the SRAM cells. A first FET is connected to Vcc, bitline load gates of the SRAM cell, and test mode operation control logic. A second FET is connected to the bitline load gates, the test mode logic, and an external pin of the SRAM device. During test mode operation, the first FET disables Vcc to the bitlines, and the second FET enables the internal bitline voltage levels to be modulated by a voltage supply received through the external pin of the device. Modulation of the bitline voltage levels is isolated from normal operating voltage levels of peripheral circuitry such as the wordlines. An alternate embodiment provides a CMOS transmission gate in place of the second FET.

REFERENCES:
patent: 5208777 (1993-05-01), Shibata
patent: 5212442 (1993-05-01), O'Toole
patent: 5222066 (1993-06-01), Grula et al.
patent: 5255230 (1993-10-01), Chan et al.
patent: 5381373 (1995-01-01), Ohsawa

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