Electrical computers and digital processing systems: support – Computer power control – Power conservation
Reexamination Certificate
1998-03-17
2002-03-12
Wiley, David (Department: 2155)
Electrical computers and digital processing systems: support
Computer power control
Power conservation
C713S320000
Reexamination Certificate
active
06357013
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to power management in a computer system, and more particularly, to power management circuitry that drives bus signals in the computer system to predetermined states in low power mode.
2. Description of the Related Art
Personal computers are constantly evolving to provide the user with the highest performance available at the lowest cost. Performance improvements in the microprocessor and memory systems have resulted in computers so powerful that they are now capable of performing tasks that before could only be performed by large mainframe computers. Technological change is especially exemplified in the area of portable computers where power consumption efficiency is balanced against features, cost, size, weight and performance. This is especially challenging since many computer users desire the portable computer to provide nothing less than what a desktop unit can provide. In this specification, the term “portable computer” is used broadly to denote the class of computers powered by battery or solar power. Those familiar with portable computers will recognize labels such as: portable, luggable, laptop, notebook and handheld which are used to designate certain marketing segments of the larger portable computer market.
Many options are available to the computer system designer. While simply designing around the highest performance processor available will go a long way towards providing a high performance product, in today's competitive market that is not enough. The processor must be supported by high performance components including a high performance I/O bus. Several standardized I/O buses are available to the system designer including: ISA (Industry Standard Architecture); EISA (Extended Industry Standard Architecture); and PCI (Peripheral Component Interface). Today's computers are typically designed with some combination of the three buses to provide the user with the performance of the PCI bus and backward compatibility to the ISA bus. These three buses are familiar to those skilled in the art and need not be described further here. However, more details on the PCI bus are found in the PCI Local Bus Specification, Production Version, Revision 2.1, dated Jun. 1, 1995, which is published by the PCI Special Interest Group of Hillsboro, Oreg., and which is hereby incorporated by reference in its entirety.
One of the problems associated with battery-powered portable computer systems is battery life. Many solutions have been proposed to reduce power consumption of a portable computer system, particularly when the system is not in use. For example, U.S. Pat. No. 4,980,836, entitled “Apparatus for Reducing Computer System Power Consumption,” describes power management circuitry which monitors for peripheral device inactivity. If a predetermined time elapses without any peripheral device activity, the computer system enters into standby mode to reduce power consumption.
With improved integrated circuit processing technology, system components have become ever more sophisticated. Increasingly, ASICs are used in computer systems to integrate bus control, bus arbitration, bus bridging, memory control, and cache control functions. As a result, power management logic can now be incorporated into these ASICs to achieve better power management schemes.
SUMMARY OF THE PRESENT INVENTION
A circuit according to the present invention performs power management functions in a computer system. The computer system has a PCI bus and an ISA bus and includes a CPU-PCI bridge connected between the host bus and the PCI bus and a PCI-ISA bridge connected between the PCI bus and the ISA bus. Preferably, the power management circuit is located in the CPU-PCI bridge. The computer system preferably implements four power levels: RUN mode for normal computer operation; SLEEP mode in which the clock to the central processing unit (CPU) is turned off; IDLE mode in which the internal clocks of the CPU, L
2
cache memory, data buffers between the processor bus and the PCI bus, and the CPU-PCI bridge are turned off; and STANDBY mode which is the same as IDLE mode except that the internal clock of the PCI-ISA bridge is also turned off. RUN mode is the highest power consumption level and STANDBY mode is the lowest power consumption level.
According to one aspect of the present invention, the power management circuit transitions from SLEEP mode to IDLE mode by first determining if the CPU-PCI bridge is parked on the PCI bus and if it is in SLEEP mode. By default, if there are no other bus requests for the PCI bus, the PCI arbiter parks the CPU-PCI bridge on the PCI bus. The power management circuit then forces one refresh operation and then waits for all internal queues to empty before checking again to determine if the CPU-PCI bridge is still parked on the PCI bus and if it is still in SLEEP mode. If true, then the CPU-PCI bridge begins to transition to IDLE mode. By entering into IDLE mode this way, an extra pin is not needed to notify the power management circuit in the CPU-PCI bridge to enter IDLE mode. As a result, a pin is saved on the chip used to implement the CPU-PCI bridge.
Once the CPU-PCI bridge enters into IDLE mode, its core logic is shut off. Preferably, one portion of that core logic is the memory controller for controlling main memory, which is implemented with dynamic random access memories (DRAMs). As it is disabled in IDLE mode, the memory controller is no longer able to perform memory refresh cycles to main memory. Thus, according to another aspect of the present invention, the power management circuit performs memory refresh cycles based off an external asynchronous clock, which is preferably the clock signal used to run the real time clock (RTC). The advantage offered by the power management circuit according to this other aspect of the present invention is that the memory controller portion of the CPU-PCI bridge can be disabled to conserve power while still allowing refresh cycles to continue.
One characteristic of the PCI bus is that it is defined as a 5-volt bus. As more and more computer system peripheral components are now implemented as 3.3-volt parts, it is possible that a mixture of 3.3-volt and 5-volt parts are connected to the PCI bus. The 3.3-volt parts are capable of driving bus signals to a high of only about 3.3 volts, whereas the 5-volt parts contain input buffer circuitry which operate from the 5-volt power supply voltage. In the present computer system, the CPU-PCI bridge is preferably a 3.3-volt component with at least one other component on the PCI bus being a 5-volt part. In the IDLE and STANDBY modes, the CPU-PCI bridge is the owner of the PCI bus, and thus it has the responsibility of driving the PCI bus signals. As the input buffer circuitry in the 5-volt component works off a 5-volt supply voltage, leakage current would occur in the input buffer circuitry if received bus signals are at 3.3 volts. Thus, according to yet another aspect of the present invention, the power management circuit in the CPU-PCI bridge drives certain of the PCI bus signals to the zero state to prevent leakage current in the 5-volt component, thereby reducing power consumption in the IDLE and STANDBY modes.
REFERENCES:
patent: 4980836 (1990-12-01), Carter et al.
patent: 5471625 (1995-11-01), Mussemann et al.
patent: 5517650 (1996-05-01), Bland et al.
patent: 644 475 (1994-12-01), None
DeSchepper Todd J.
Kelly Philip C.
Reif James R.
Compaq Computer Corporation
Sharp Comfort & Merrett P.C.
Wiley David
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