Circuit for reducing transient simultaneous conduction

Details Circuit for reducing transient simultaneous conduction Circuit for reducing transient simultaneous conduction

1993-09-24

1995-05-23

Hudspeth, David R.

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Output switching noise reduction

326 81, H03K 1716

Patent

active

054184746

ABSTRACT:
A transient-eliminating circuit for minimizing simultaneous conduction through the pullup and pulldown transistors of a buffer circuit. In a buffer circuit used to translate logic signals from circuits supplied by one high-potential power rail to circuits supplied by another high-potential power rail, in which the potentials of the two high-potential rails are not equal, the transient-eliminating circuit is coupled between the output stage and the input stage in such a way that the translator can be utilized independent of power-up sequencing and without any static current I.sub.CCt. The transient-eliminating circuit minimizes simultaneous conduction through the pullup and pulldown transistors of the translator by delaying the turn-on of the pulldown transistor until the pullup transistor is completely off. This is achieved in the preferred embodiment of the invention by coupling an NMOS transistor to the output of the translator circuit to act as an early pulldown on the output by using that NMOS transistor to control a PMOS transistor which is in turn used to control the pulldown transistor. A second NMOS transistor of the transient-eliminating circuit also acts to control the pulldown transistor by operating in the reverse mode of the first NMOS transistor so as to ensure that the NMOS transistor is completely off when required.

REFERENCES:
patent: 4818401 (1989-04-01), Young et al.
patent: 5036222 (1991-07-01), Davis
patent: 5220209 (1993-06-01), Seymour
patent: 5280203 (1994-01-01), Hung et al.
patent: 5300832 (1994-04-01), Rogers
patent: 5315173 (1994-05-01), Lee et al.

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