Circuit for reducing the row select voltage swing in a memory ar

Details Circuit for reducing the row select voltage swing in a memory ar Circuit for reducing the row select voltage swing in a memory ar

1985-11-22

1988-03-08

Popek, Joseph A.

Static information storage and retrieval

Systems using particular element

Semiconductive

365190, 365155, 365176, 307449, G11C 700

Patent

active

047302755

ABSTRACT:
A circuit reduces the row select voltage swing in a memory array, thereby reducing access time, power dissipation, disturb problems, glitches on the output, and alpha particle sensitivity. A row driver transistor is coupled between a first voltage source and the word line of a row of memory cells and has a base coupled to a row decode signal. A clamp circuit coupled to the base clamps a voltage on the base in accordance with a current provided by a current mirror coupled thereto. A write enable circuit is differentially connected to the current mirror and the clamp circuit for enabling the clamp circuit during a read mode for limiting the voltage swing on the word line.

REFERENCES:
patent: 4460984 (1984-07-01), Knepper
patent: 4646268 (1987-02-01), Kuro

Affiliated with

Also associated with

Rating

Circuit for reducing the row select voltage swing in a memory ar does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Circuit for reducing the row select voltage swing in a memory ar, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit for reducing the row select voltage swing in a memory ar will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-233926