Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2001-05-01
2004-08-17
Chung, Phung M. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S736000
Reexamination Certificate
active
06779139
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a test facilitating circuit and a semiconductor memory device including the circuit, and particularly, to a configuration for testing whether or not data coincides with an expected value.
2. Description of the Background Art
A memory combined with a logic having a wide I/O (input/output) bus has heretofore available. Such a logic combined memory is provided with a circuit for testing a memory.
To be concrete, the testing includes a saving test detecting a defective memory cell and a functional test testing a memory after a defective memory cell is replaced with a redundant memory cell.
In the saving test, it is specified where a failure has arisen. In the functional test, it is determined that a chip under test is defective if any of read data has a fail.
In the mean time, since a memory combined with a logic having a wide I/O bus has a limitation on the number of output pins for testing, a necessity arises that read data read out from memory cells or determination results (pass/fail) each showing coincidence
on-coincidence between read data and an expected value are divided into groups for outputting in times.
In a functional test following a saving test, since determination results can be degenerated (without specifying a failure) for outputting, using means such as a multibit test, a test time can be reduced in spite of presence of the above described limitation.
In a saving test, however, since it is necessary to specify a place of a failure, no means is adopted to degenerate and output a determination result.
More concrete description will be given of a saving test for a prior art semiconductor memory device (a logic combined memory) using
FIGS. 25 and 26
. Note that
FIGS. 25 and 26
use the same abscissa representing a time scale with the same time point t1 thereon. An I/O bus width for use in simultaneous outputting is set to 256 (a 256 I/O configuration). Data input/output pins D/Q each selected as one from every 32 I/O adjacent to each other. Therefore, 8 data I/O pins are assigned to test output pins for the 256 I/O.
It is assumed that word lines have a branched word line configuration and one main word line MWL branches out into 4 subword lines SWL. Furthermore, one of 16 columns (16 sense amplifiers) is connected to one data I/O bus pair according to a column select signal. Moreover, spare substitution in a row direction is performed with one MWL as a unit, while spare substitution in a column direction is performed with one I/O as a unit. In the substitution, all of memory cells connected to a prescribed region (of one MWL and one I/O) are replaced at a time.
Commands specifying internal operations (ACT, NOP, Read and PRE) are each issued at each rise of a clock signal CLK and addresses for word line selection and column selection are inputted at the rise of the clock signal CLK on each of the issuance. CSLi indicates a column select signal and Dk indicates read data.
For example, a subword line SWL
0
of a main word line MWL
0
is selected and data is successively transmitted onto an I/O bus I/O
0
according to column select signals CSL
0
to CSL
15
. Data is outputted from a data I/O output pin DQ<0> connected to the bus. A similar operation is repeated for 32 sets (corresponding to I/O
0
to I/O
31
).
Subsequent to this, data on memory cells connected to the subword lines SWL
1
, SWL
2
and SWL
3
is successively read out.
In such a fashion, in the prior art saving test, it is necessary that data is written into a memory array block at a time via 256 I/O simultaneously inputtable and thereafter, the data written thereinto is all read out, or determination results showing coincidence
on-coincidence between expected values and the read data are divided into 32 groups (=256/8) to output.
Accordingly, in the above example, a period required for reading out data of the subword line SWL
0
is (ACT+NOP+16 Read×32+NOP+PRE+NOP)=517 cycles. Hence, in order to read out all the data connected to one MWL and one I/O in the 256 I/O configuration, a time length of 517×4=2068 cycles is required.
On the other hand, in a functional test, determination results can be degenerated and outputted as described above. However, for example, when functional tests for many chips are performed in parallel while the chips are inserted in a burn-in board as in Testing Burn-In, it is required that test results are successively loaded onto a bus on the board. Furthermore, when a test is performed on a chip on which PLL and the like circuits are mounted using a low speed tester, a stroboscope for determination can not work properly even if test results are outputted to outside at high speed using PLL or the like, due to use of the low speed tester.
SUMMARY OF THE INVENTION
It is accordingly an object of the present invention to provide a test facilitating circuit capable of testing a data value in a short time with ease.
A test facilitating circuit according to an aspect of the present invention includes a non-coincidence holding circuit receiving a determination result showing coincidence
on-coincidence between input data and an expected value and a control signal at an input thereof, wherein when the control signal shows a transmission state, the non-coincidence holding circuit catches the determination result, while when the control signal shows an accumulation state different from the transmission state, once the non-coincidence holding circuit catches the determination result showing the non-coincidence, thereafter the non-coincidence holding circuit holds the determination result showing the non-coincidence till the control signal shows the transmission state.
It is preferable that a plurality of non-coincidence holding circuits are provided and the test facilitating circuit further includes: a plurality of comparators each determining coincidence
on-coincidence between input data and an expected value. Each of the plurality of non-coincidence holding circuits receives a determination result outputted by a corresponding comparator.
Particularly, the test facilitating circuit further includes: a circuit outputting a non-coincidence result when at least one of first plural ones of the determination results is the non-coincidence; and a degeneration circuit outputting the non-coincidence result when the circuit outputs the non-coincidence result.
It is preferable that the test facilitating circuit further includes: a multibit test circuit testing whether or not all of bits of the data are in coincidence, wherein the non-coincidence holding circuit receives an output of the multibit test circuit as the determination result.
It is preferable that the test facilitating circuit further includes: a saving circuit catching the determination result outputted by the non-coincidence holding circuit when a shift signal is in a first state, while holding the determination result caught at a previous time when the shift signal is in a second state other than the first state.
Particularly, the non-coincidence holding circuit receives the shift signal as the control signal.
It is preferable that a plurality of non-coincidence holding circuits and a plurality of saving circuits including the saving circuit are provided and the test facilitating circuit further includes: a circuit outputting a non-coincidence result when at least one of the plurality of first determination results; and a degeneration circuit outputting the non-coincidence result when the circuit outputs the non-coincidence circuit.
Particularly, the test facilitating circuit further includes a counter generating a control signal or a shift signal. The test facilitating circuit further includes a circuit catching an expected value in a specified operating mode only.
According to a test facilitating circuit relating to the present invention, by providing an accumulation section accumulating coincidence
on-coincidence results between data and expected values, determination results can be
Dosaka Katsumi
Haraguchi Masaru
Tanizaki Tetsushi
Chung Phung M.
McDermott Will & Emery LLP
Renesas Technology Corp.
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