Circuit for reducing second order intermodulation

Telecommunications – Receiver or analog modulated signal frequency converter – Local control of receiver operation

Reexamination Certificate

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C455S318000, C455S323000

Reexamination Certificate

active

07421263

ABSTRACT:
A circuit for calibrating a second order intercept point (IP2) and for reducing second order intermodulation (IM2) includes a common mode feedback circuit and a load impedance operatively connected between first and second output terminals of a mixer in a direct conversion receiver. The common mode feedback circuit reduces second order intermodulation of the mixer by detecting an output voltage of the mixer and adjusting a gain of the mixer. The IP2 is controlled by controlling the gain of the common mode feedback circuit. The second order intermodulation (IM2) may be reduced and the linearity of a device may be enhanced.

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patent: 2003/0129958 (2003-07-01), Behzad
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patent: WO 02/33812 (2002-04-01), None
Baker, Jacob R., Li, Harry W., Boyce, David E. “CMOS Circuit Design, Layout, and Simulation,” IEEE, ISBN 0-7803-3416-7, 1998, pp. 666-668.

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