Circuit for receiving and driving a clock-signal

Details Circuit for receiving and driving a clock-signal Circuit for receiving and driving a clock-signal

2000-11-30

2002-12-03

Le, Don Phu (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C326S087000, C326S027000

Reexamination Certificate

active

06489809

ABSTRACT:

BACKGROUND
1. Technical Field
This disclosure relates to receiver circuits, and more particularly, to a receiver circuit adapted to both receive and drive signals which is immune from noise superimposed to a signal during or after a signal transition.
2. Description of the Related Art
Digital circuits may be subject to noisy signals. Noisy signals may result in bit errors when converting the analog waveforms to digital signals. Noise suppression can reduce noise. For example, in receiver circuits that convert (noisy) analog input signals to digital on-chip signals, hysteresis is one means to suppress noise. Instances of slope reversal caused by reflections on ill terminated signal traces and extremely slow transitions (e.g., in burn-in test setups for semiconductor device tests) superimposed with random noise can cause incomplete pulses and spikes of the on-chip digital signals. This can cause malfunction of circuitry that assumes certain minimum and maximum pulse widths.
A structure of a differential amplifier-based receiver is shown in
FIG. 1. A
first stage
10
includes an N-channel differential pair
11
with a P-channel current mirror
13
. A second stage
12
is realized by an inverter
14
. One advantage of this configuration is that a switch-point is very well defined by the reference voltage VREF. The switch-point is the input voltage level (VIN) at which the output switches. For good system performance, a hysteresis of about 5-10% of the input voltage (VIN) swing is desirable. For stub series terminated logic (SSTL-2, for example), this would be a few tens of mV's.
In a conventional clock path, a clock signal is first converted to CMOS levels by receiver circuit
10
. The CMOS levels are fed into a driving stage
20
which is capable of driving a large capacitive internal load of several pF's (e.g., (C
load
)
Driver stage
20
shapes the pulses to fine tune them for use by other circuits. Driver stage
20
may include an inverter driver stage, a self-reset skewed one-shot pulse shaper or a dual skewed driver stage (e.g. as shown in U.S. Pat. No. 5,128,555). Driver stage
20
requires a noise-free CMOS signal at its input to function properly.
Therefore, a need exists for a circuit which incorporates both receiver and driver functions in a single unit to reduce the overall delay and power consumption over prior art solutions.
SUMMARY OF THE INVENTION
A receiver circuit includes a first circuit having two modes of operation controlled by a feedback loop. The feedback loop is connected to an output of the first circuit, and the modes of operation include a first mode having a quicker response to an input falling signal edge than a second mode and a second mode with a quicker response to an input rising signal edge than the first mode. A driver stage is integrated into the first circuit to favor the rising edge or the falling edge in accordance with a control signal provided by the feedback loop.
In other embodiments, the driver stage may include an inverter chain. The inverter chain preferably includes NMOS and PMOS transistors, the NMOS and the PMOS transistors having skewed strengths to favor one of the rising and falling edges. The driver stage is preferably capable of driving digital and analog signals input thereto. At least one current source is preferably coupled to the driver stage to provide driving current to the output in accordance with the control signal. The first circuit may include a switching circuit having switching elements switched by the control signal to alternately select circuit elements which favor a rising edge and a falling edge. The first circuit may include a differential amplifier. The feedback loop may include delay elements such that noise after a transition in the input signals is suppressed for a delay period provided by the delay elements. The feedback loop may be programmable to adjust the delay period provided by the delay elements. The feedback loop may be controlled by a control circuit to adjust the delay period provided by the delay elements. The delay period may be controlled in accordance with an input signal input to the receiver circuit.
Another receiver circuit includes a first stage having an input for receiving input signals and an output node, the first stage including an amplifier. A second stage has an input coupled to the output of the first stage. The second stage includes a switching circuit coupled to the output node of the first stage for driving the input signals by favoring one of a rising edge or a falling edge in accordance with a control signal. A feedback loop is coupled to an output of the second stage, the feedback loop providing the control signal for switching the switching circuit to favor the rising edge or falling edge. At least one driver stage is integrated into the second stage and coupled to the switching circuit for favoring the rising edge or the falling edge in accordance with the control signal.
In other embodiments, the second stage may include an inverter coupled to the output of the first stage, the inverter having an output representing the output of the receiver circuit. The second stage may include a first transistor coupled between the output of the inverter and a supply voltage and a second transistor coupled between the output of the inverter and a ground, wherein the first and second transistors have different strengths relative to transistors of the inverter to provide skewed driver strength for driving the input signals to the output of the second stage. The at least one driver stage may include a first driver stage coupled to a gate of the first transistor and coupled to the switching circuit. The at least one driver stage may include a second driver stage coupled to a gate of the second transistor and coupled to the switching circuit. The second stage may include at least one current source coupled to the at least one driver stage to provide driving current to a gate of one of the first and second transistors through the at least one driver stage in accordance with the control signal.
In still other embodiments, the switching circuit may include switching elements switched by the control signal to alternately select circuit elements which favor a rising edge and a falling edge. The switching elements may include CMOS transfer gates. The amplifier may include a differential amplifier. The amplifier may include a transconductance amplifier. The input signals may include analog signals and the receiver circuit preferably suppresses noise of the analog signals. The output preferably represents a digital logic state. The feedback loop may include delay elements such that noise after a transition in the input signals is suppressed for a delay period provided by the delay elements provided by the delay elements. The feedback loop may be programmable to adjust the delay period provided by the delay elements. The feedback loop may be controlled by a control circuit to adjust the delay period provided by the delay elements. The delay period may be controlled in accordance with an input signal input to the receiver circuit. A delay value of the delay elements may be less than half a clock period of the input signal. The at least one driver stage may include an inverter chain. The inverters of the inverter chain may include transistors, the inverters of the inverter chain having transistor strengths skewed relative to another inverter of the inverter chain to amplify one of the rising edge and the falling edge.
Another receiver circuit includes a first stage having an input for receiving input signals and an output node, the first stage including an amplifier. A second stage has an input coupled to the output of the first stage. The second stage includes an inverter coupled to the output of the first stage, the inverter having an output representing the output of the receiver circuit and including transistors, a first transistor coupled between the output of the inverter and a supply voltage, a second transistor coupled between the output of the inverter and a ground, wherein the

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