Circuit for providing a reading phase after power-on-reset

Details Circuit for providing a reading phase after power-on-reset Circuit for providing a reading phase after power-on-reset

1999-04-20

2000-12-05

Elms, Richard

Static information storage and retrieval

Read/write circuit

Including signal comparison

36518909, 365226, 36523008, G11C 1604

Patent

active

061575798

ABSTRACT:
A circuit for providing a first reading phase after a Power-On-Reset in a memory device. The circuit includes a comparator, a reference generator that generates a reference voltage signal that is supplied to one input of the comparator, and a voltage divider that generates an output signal that is supplied to another input of the comparator. The reference voltage signal reaches its steady operational value before the supply voltage, and the output signal has the same linear pattern as the supply voltage with a different angular coefficient. The comparator outputs a control signal for starting the first reading phase of the memory device. In one preferred embodiment, the memory device has a single power supply and a zero consumption standby mode. Additionally, there is provided a method for providing a first reading phase after a Power-On-Reset in a memory device. According to the method, a reference voltage signal and a proportional voltage signal are generated and compared so as to generate a control signal for starting the first reading phase of the memory device. The generated reference voltage signal reaches its steady operational value before the supply voltage, and the generated proportional voltage signal has the same linear pattern as the supply voltage with a different angular coefficient.

REFERENCES:
patent: 4531214 (1985-07-01), Torres et al.
patent: 5301161 (1994-04-01), Landgraf et al.
patent: 5812017 (1998-09-01), Golla et al.

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