Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
2000-09-05
2002-04-02
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S044000, C326S040000, C326S049000
Reexamination Certificate
active
06366128
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to methods and circuits for providing high-speed, low-voltage differential signals.
BACKGROUND
The Telecommunications Industry Association (TIA) published a standard specifying the electrical characteristics of low-voltage differential signaling (LVDS) interface circuits that can be used to interchange binary signals. LVDS employs low-voltage differential signals to provide high-speed, low-power data communication. The use of differential signals allows for cancellation of common-mode noise, and thus enables data transmission with exceptional speed and noise immunity. For a detailed description of this LVDS Standard, see “Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits,” TIA/EIA-644 (March 1996), which is incorporated herein by reference.
FIG. 1
(prior art) illustrates an LVDS generator
100
connected to an LVDS receiver
110
via a transmission line
115
. Generator
100
converts a single-ended digital input signal D_IN on a like-named input terminal into a pair of complementary LVDS output signals on differential output terminals TX_A and TX_B. A 100-ohm termination load RL separates terminals TX_A and TX_B, and sets the output impedance of generator
100
to the level specified in the above-referenced LVDS Standard.
LVDS receiver
110
accepts the differential input signals from terminals TX_A and TX_B and converts them to a single-ended output signal D_OUT. The LVDS Standard specifies the properties of LVDS receiver
110
. The present application is directed to differential-signal generators: a comprehensive discussion of receiver
110
is not included in the present application.
FIG. 2
(prior art) schematically depicts LVDS generator
100
of FIG.
1
. Generator
100
includes a preamplifier
200
connected to a driver stage
205
. Preamplifier
200
receives the single-ended data signal D_IN and produces a pair of complementary data signals D and D/ (signal names terminating in “/” are active low signals). Unless otherwise specified, each signal is referred to by the corresponding node designation depicted in the figures. Thus, for example, the input terminal and input signal to generator
100
are both designated D_IN. In each instance, the interpretation of the node designation as either a signal or a physical element is clear from the context.
Driver stage
205
includes a PMOS load transistor
207
and an NMOS load transistor
209
, each of which produces a relatively stable drive current in response to respective bias voltages PBIAS and NBIAS. Driver stage
205
additionally includes four drive transistors
211
,
213
,
215
, and
217
.
If signal D_IN is a logic one (e.g., 3.3 volts), preamplifier
200
produces a logic one on terminal D and a logic zero (e.g., zero volts) on terminal D/. The logic one on terminal D turns on transistors
211
and
217
, causing current to flow down through transistors
207
and
211
, up though termination load RL, and down through transistors
217
and
209
to ground (see the series of arrows
219
). The current through termination load RL develops a negative voltage between output terminals TX_A and TX_B.
Conversely, if signal D_IN is a logic zero, preamplifier
200
produces a logic zero on terminal D and a logic one on terminal D/. The logic one on terminal D/ turns on transistors
213
and
215
, causing current to flow down through transistor
207
, transistor
215
, termination load RL, transistor
213
, and transistor
209
to ground (see the series of arrows
221
). The current through termination load RL develops a positive voltage between output terminals TX_A and TX_B.
FIG. 3
(prior art) is a waveform diagram
300
depicting the signaling sense of the voltages appearing across termination load RL of
FIGS. 1 and 2
. LVDS generator
100
produces a pair of differential output signals on terminals TX_A and TX_B. The LVDS Standard requires that the voltage between terminals TX_A and TX_B remain in the range of 250 mV to 450 mV, and that the voltage midway between the two differential voltages remains at approximately 1.2 volts. Terminal TX_A is negative with respect to terminal TX_B to represent a binary one and positive with respect to terminal B to represent a binary zero.
A programmable logic device (PLD) is a well-known type of IC that may be programmed by a user (e.g., a circuit designer) to perform specified logic functions. Most PLDs contain some type of input/output block (IOB) that can be configured either to receive external signals or to drive signals off chip. One type of PLD, the field-programmable gate array (FPGA), typically includes an array of configurable logic blocks (CLBS) that are programmably interconnected to each other and to the programmable IOBs. Configuration data loaded into internal configuration memory cells on the FPGA define the operation of the FPGA by determining how the CLBS, interconnections, block RAM, and IOBs are configured.
IOBs configured as output circuits typically provide single-ended logic signals to external devices. As with other types of circuits, PLDs would benefit from the performance advantages offered by driving external signals using differential output signals. There is therefore a need for IOBs that can be configured to provide differential output signals. There is also a need for LVDS output circuits that can be tailored to optimize performance for different loads.
SUMMARY
The present invention addresses the need for differential-signal output circuits that can be tailored for use with different loads. In accordance with one embodiment, one or more driver stages can be added, as necessary, to provide adequate power for driving a given load. Driver stages are added by programming one or more programmable elements, such as memory cells, fuses, and antifuses.
A differential driver in accordance with another embodiment includes a multi-stage delay element connected to a number of consecutive driver stages. The delay element produces two or more pairs of complementary input signals in response to each input-signal transition, each successive signal pair being delayed by some amount relative to the previous signal pair. The pairs of complementary signals are conveyed to respective driver stages, so that each driver stage successively responds to the input-signal transition. The output terminals of the driver stages are connected to one another and to the output terminals of the differential driver. The differential driver thus responds to each input-signal transition with increasingly powerful amplification. The progressive amplification produces a corresponding progressive reduction in output resistance, which reduces the noise normally associated with signal reflection.
Extendable and multi-stage differential amplifiers in accordance with the invention can be adapted for use in PLDs. In one embodiment, adjacent pairs of IOBs are each provided with half of the circuitry required to produce LVDS signals. Adjacent pairs of IOBs can therefore be used either individually to provide single-ended input or output signals or can be combined to produce differential output signals.
This summary does not limit the invention, which is instead defined by the appended claims.
REFERENCES:
patent: 5355035 (1994-10-01), Vora et al.
patent: 5812461 (1998-09-01), Komarek et al.
patent: 5958026 (1999-09-01), Goetting et al.
patent: 60260254 (1987-06-01), None
Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits, TIA/EIA-644, Mar. 1996.
Jon Brunetti and Brian Von Herzen, “Multi-Drop LVDS with Virtex-E FPGAs,” XAPP231 (Version 1.0) Sep. 23, 1999.
Application Report “LVDS Multidrop Connections” published by Texas Instruments, Jul. 1999.
Ghia Atul V.
Menon Suresh M.
Schultz David P.
Behiel Arthur J.
Chang Daniel D.
Tokar Michael
Xilinx , Inc.
Young Edel M.
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