Circuit for prevention of the metastable state in flip-flops

Details Circuit for prevention of the metastable state in flip-flops Circuit for prevention of the metastable state in flip-flops

1983-12-02

1986-03-11

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307269, 307272R, 307480, 328164, 328206, H03K 329, H03K 513

Patent

active

045756449

ABSTRACT:
A synchronizing circuit using a switchable bistable element for synchronizing an asymmetric signal with the clock of a data processing system. The occurrence of a balanced or metastable state in the switchable bistable synchronizing element which can slow up the data transfer rate is inhibited by applying an asymmetric injection signal thereto having a frequency, magnitude and asymmetry such that the maintenance of a balanced or metastable state in the synchronizing element is inhibited without interfering with the normal switching operation thereof.

REFERENCES:
patent: 3921011 (1975-11-01), Orgill
patent: 4048521 (1977-09-01), Thompson et al.
patent: 4093878 (1978-06-01), Paschal et al.
"Theoretical and Experimental Behavior of Synchronizers Operating in the Metastable Region", IEEE Transactions on Computers, vol. C-24, No. 6, Jun. 1975, pp. 604-615, by G. R. Louranz.
"Anomalous Behavior of Synchronizer and Arbiter Circuits", IEEE Transactions on Computers, Apr. 1973, pp. 421-422, by T. J. Chaney et al.

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