Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
1999-10-26
2001-06-05
Dharia, Rupal (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S108000, C365S189050, C365S230060, C365S233100, C365S236000
Reexamination Certificate
active
06243777
ABSTRACT:
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not Applicable.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is directed generally to a circuit for preventing bus contention, and, more particularly, to preventing bus contention problems in solid state stacked memories.
2. Description of the Background
In computer circuits, stacking is a process by which a number of relatively small devices are combined in a manner so that the small devices, collectively, emulate a larger device. Stacking can be either depth-expanded or width-expanded. In a simple example of stacking involving a random access memory (RAM), eight 1-bit RAMs, each having an input terminal, an output terminal, and an enable terminal, may be combined to emulate a single, 8-bit RAM. In such a case, the input terminals of each 1-bit RAM are tied together to form a common input terminal for the 8-bit RAM. Likewise, the output terminals of each 1-bit RAM are tied together to form a common output terminal for the 8-bit RAM.
For the collective device to function properly, only one individual 1-bit RAM can read or write from the shared terminals at any given time. That is typically accomplished by using logic circuits to decode address data and to provide an enable signal to only one 1-bit RAM at any given time.
Bus contention occurs when more than one device attempts to transmit information on the data bus at the same time. Bus contention can result when RAMs manufactured by different companies are stacked. That is because significant variations in timing parameters and tolerances exist between manufacturers.
The most visible result of bus contention is noise on power-supply lines and data lines connecting the devices. Another result of bus contention is loss of data during the period of contention. If one RAM is trying to drive the data bus high, while another RAM is trying to drive the data bus low, then the RAMs will be working against each other, data will be lost, and components in the circuit may be damaged from excessive current, known as “overcurrent”. CMOS latch-up can result if the overcurrent is sufficiently high. If bipolar devices are used, damage can result because bipolar devices are not inherently self-current limiting. As a result, a feedback cycle can be initiated in which current through a bipolar transistor increases, the transistor heats up and its gain increases, causing further increases in current, heat, and gain. A phenomenon known as “thermal runaway” occurs when that feedback cycle results in current reaching a destructive level.
In the past, such bus contention could be avoided by insuring that all RAMs used in a stacking arrangement were manufactured by the same company, thereby ensuring nearly identical performance from all devices. Presently, however, bus contention is becoming a significant concern even when RAMs from the same manufacturer are used. That is because clock speeds are increasing to the point that even the manufacturing tolerances between RAMs from the same manufacturer are significant enough to cause bus contention in a stacked RAM array. In other words, the margin of error in modern computers has decreased to the point that the variations that occur between RAMs in the same manufacturing process are sufficient to cause bus contention. Thus, the need exists for a device to eliminate bus contention problems.
SUMMARY OF THE INVENTION
The present invention is directed to a circuit for controlling the data transmissions among two devices capable of transmitting information, via an output buffer, over a bus, so as to prevent bus contention. The circuit is comprised of a first device enabled circuit for generating a first device enabled signal indicative of whether one of the devices is enabled to transmit information. A second device enabled circuit generates a second device enabled signal indicative of whether the other of the devices is enabled to transmit information. A circuit, which is in communication with the first and second device enabled circuits, generates an output enable signal. The output enable signal is input to one of the devices to create a delay between the end of a transmission of information by one device and the beginning of a transmission by the other device.
The circuit of the present invention may be carried onboard a memory device. The memory device is comprised of a first device enabled circuit for generating a first device enabled signal indicative of whether the memory device is enabled to transmit information. A second device enabled circuit generates a second device enabled signal indicative of whether another device is enabled to transmit information. A control circuit, in communication with the first and second device enabled circuits, generates an output enable signal to create a delay between the end of a transmission of information by another device and the beginning of a transmission of data by the memory device. The memory device additionally comprises a memory array, a circuit for receiving information from a data bus, a circuit for writing, responsive to the circuit for receiving, for writing information to the memory array, a circuit for reading information from the memory array, and an output circuit for transmitting, responsive to both the circuit for reading information and the control circuit, for transmitting information on the data bus.
The present invention solves the problem of bus contention between stacked RAMs by providing a delay between the beginning of a transmission by one device and the end of a transmission by another device. For example, by providing an additional clock cycle between the time one stacked RAM is expected to stop driving the data bus and when another stacked RAM is expected to begin driving the data bus, bus contention is eliminated. In that way, bus contention that would be caused by one stacked RAM driving the data bus too late, or by one stacked RAM driving the data bus too soon, or both, is avoided by a one clock cycle buffer between the transition from one stacked RAM to another. Those and other advantages and benefits of the present invention will become apparent from the description of the preferred embodiments hereinbelow.
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patent: 5384737 (1995-01-01), Childs et al.
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Author Unknown, 1993,1994 SRAM Data Book, pp. 5-9 to 5-12, USA.
Dharia Rupal
Kirkpatrick & Lockhart LLP
Micro)n Technology, Inc.
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