Circuit for preventing bus contention

Details Circuit for preventing bus contention Circuit for preventing bus contention

1995-12-19

2000-05-02

Sheikh, Ayaz R.

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

710108, 36523006, 365233, 365236, 36518905, G06F 1336

Patent

active

060584483

ABSTRACT:
A circuit for controlling the data transmissions among two devices capable transmitting information, via an output buffer, over a bus, so as to prevent bus contention, is comprised of a first device enabled circuit for generating a first device enabled signal indicative of whether one of the devices is enabled to transmit information. A second device enabled circuit generates a second device enabled signal indicative of whether the other of the devices is enabled to transmit information. A circuit, which is in communication with the first and second device enabled circuits, generates an output enable signal. The output enable signal is input to one of the devices to create a delay between the end of a transmission of information by one device and the beginning of a transmission by the other device.

REFERENCES:
patent: 5086427 (1992-02-01), Whittaker et al.
patent: 5313594 (1994-05-01), Wakerly
patent: 5384737 (1995-01-01), Childs et al.
patent: 5416739 (1995-05-01), Wong
patent: 5428797 (1995-06-01), Yamamura et al.
patent: 5444858 (1995-08-01), Wakerly
patent: 5548728 (1996-08-01), Danknick
patent: 5553246 (1996-09-01), Suzuki
patent: 5559753 (1996-09-01), Kocis
Author unknown, 1993, 1994 SRAM Data Book, pp. 5-9 to 5-12, USA.

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