Circuit for placing a cache memory into low power mode in respon

Details Circuit for placing a cache memory into low power mode in respon Circuit for placing a cache memory into low power mode in respon

1996-08-28

1998-09-22

Swann, Tod R.

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

Addressing cache memories

364DIG1, 364DIG2, 3642434, 365227, 36518907, 36523003, 39575003, 39575005, 711118, 711143, 711146, 711167, G06F 1200, G06F 132

Patent

active

058130225

ABSTRACT:
A circuit for placing an external or L2 cache memory into low power mode in response to certain special cycles executed by the microprocessor. In particular, the special cycles are the stop grant acknowledge special cycle and the halt special cycle. The microprocessor executes the stop grant acknowledge special cycle in response to a request by the computer system to slow down its clock. This request is asserted by the computer system if the system has been idle for a predetermined period of time. The halt special cycle is generated by the microprocessor when a HALT instruction is executed. The stop grant acknowledge and halt special cycles place the microprocessor into a low power state. Since the microprocessor is in low power mode, the L2 cache memory is also placed into low power mode for further power conservation. The L2 cache memory is implemented either with synchronous or asynchronous static random access memories (SRAMs). To place a synchronous SRAM into low power mode, its address strobe input is asserted while its chip select input is deasserted. For an asynchronous SRAM, deasserting its chip select input causes the SRAM to transition into low power mode.

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