Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2006-03-28
2006-03-28
Tran, Anh Q. (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S028000, C326S082000
Reexamination Certificate
active
07019555
ABSTRACT:
A circuit for performing an on-die termination operation includes a clock buffer for outputting first and second buffered clocks using an external clock and an external inverting clock applied thereto externally; an on-die termination buffer for comparing each other an ODT signal and a reference voltage, which are applied thereto from an external chip set, to generate an on-die termination comparison signal; a first flip-flop member for transferring the on-die termination comparison signal as a plurality of parallel output signals based on the first and second buffered clocks outputted from the clock buffer; and a plurality of second flip-flop members, which corresponds to each of the parallel output signals outputted from the first flip-flop member, for transferring the parallel output signals outputted from the first flip-flop member based on delayed lock loop clocks outputted from a delayed lock loop.
REFERENCES:
patent: 6768393 (2004-07-01), Song
patent: 6917546 (2005-07-01), Matsui
Blakely & Sokoloff, Taylor & Zafman
Hynix / Semiconductor Inc.
Tran Anh Q.
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