Circuit for parity tree structure

Details Circuit for parity tree structure Circuit for parity tree structure

2007-07-10

2007-07-10

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Exclusive function

Exclusive nor

C326S052000, C326S053000, C326S055000, C327S022000, C327S023000, C327S024000, C327S025000, C327S026000, C327S027000

Reexamination Certificate

active

11221638

ABSTRACT:
A circuit for a parity tree is disclosed. In one embodiment, a circuit for a parity tree includes a pull-up circuit, a pull-down circuit, and a cross-couple circuit. The circuit, an XOR/XNOR circuit, includes both an output node and an inverted output node. For a given set of input signals, a pull-up path exists through the cross-couple circuit for one of the output node and the inverted output node, and wherein a pull-down path exists through the cross-couple circuit for the other one of the output node and the inverted output node.

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patent: 2005/0253625 (2005-11-01), Gliese et al.
patent: 2006/0181310 (2006-08-01), Rhee

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