Static information storage and retrieval – Systems using particular element – Magnetoresistive
Reexamination Certificate
2003-05-29
2004-06-08
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Systems using particular element
Magnetoresistive
C365S207000
Reexamination Certificate
active
06747891
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a circuit for non-destructive, self-normalizing reading-out of MRAM memory cells (MRAM=magnetoresistive RAM). A normal resistance value R
norm
of a memory cell is determined at a voltage at which the resistance value of the memory cell is independent of its cell content, and the actual resistance value R(0) or R(1) of the memory cell is determined at a voltage at which the resistance value of the memory cell depends on its cell content. The actual resistance value is then normalized by the normal resistance value by the equation:
R
norm
(0)=
R
(0)/
R
norm
and, respectively,
R
norm
(1)=
R
(1)/
R
norm.
R
norm
(0) and R
norm
(1) are then compared with a reference value, and in which, finally, the memory cell content is detected as a 0 or 1 on the basis of the comparison result.
A memory cell of an MRAM is shown schematically in FIG.
5
. In such a memory cell, information to be stored is stored by the type of alignment of magnetic moments in adjacent magnetized layers ML
1
and ML
2
, which are separated from each other by a very thin, nonmagnetic and nonconductive intermediate layer TL. This is because the magnitude of the electrical resistance across the memory cell depends on the parallel or anti-parallel alignment of the magnetic moments in the magnetized layers ML
1
and ML
2
, that is to say their polarization. In the case of parallel alignment of the magnetic moments in the two layers ML
1
and ML
2
, the resistance value of the memory cell is generally lower than in the case of their anti-parallel alignment. This effect is also termed the tunneling magnetoresistive (TMR) effect or the magnetic tunnel junction (MTJ) effect. A memory cell containing the layers ML
1
, TL and ML
2
is therefore also known by the name MTJ cell.
It is therefore possible for the stored content of the memory cell to be read out by detecting the resistance value of the memory cell, which is different for a “1” and “0”, respectively. Parallel magnetization of the two layers ML
1
and ML
2
can, for example, be assigned to a digital zero, the anti-parallel magnetization of these layers then corresponding to a digital one.
The resistance change between a parallel and anti-parallel alignment of the magnetic moments in the magnetized layers ML
1
and ML
2
is based physically on the interaction of the electron pins of the conduction electrons in the thin nonmagnetic intermediate layer TL with the magnetic moments in the magnetized layers ML
1
and ML
2
of the memory cell. Here, “thin” is intended to express the fact that the conduction electrons are able to cross the intermediate layer TL without spin/scattering processes.
One of the two magnetized layers ML
1
and ML
2
is preferably coupled with its magnetization to an antiferromagnetic under layer or covering layer, as a result of which the magnetization in this magnetized layer remains substantially fixed, while the magnetic moment of the other magnetized layer can be aligned freely even under small magnetic fields, such as are produced, for example, by a current in a word line WL and a bit line BL over and under the magnetized layer.
In a memory cell array, programming currents I
WL
and I
BL
through the word line WL and through the bit line BL are selected in such a way that a magnetic field which is sufficiently strong for programming, as a result of the sum of the two currents I
WL
and I
BL
, prevails only in the cell in which the word line WL crosses the bit line BL, while all the other memory cells located on the word line WL and the bit line BL cannot be reprogrammed by the current flowing only through one of these two lines.
In the lower half of
FIG. 5
, a resistance R
C
of the memory cell between the bit line BL and the word line WL is once more illustrated schematically, the resistance R
C
being greater for an anti-parallel alignment of the magnetic moments in the layers ML
1
and ML
2
than for a parallel alignment of the magnetic moments, that is to say R
C
(“0”)<R
c
(“1”), if the above assumption for the assignment of “1” and “0” is used as a basis.
In their simplest embodiment, MRAMs have conductor tracks that cross in the form of a matrix for the word lines WL and the bit lines BL, via which the memory cells are activated. An upper conductor track, for example the bit line BL (see
FIG. 5
) is in this case connected to the upper magnetized layer ML
1
, for example a ferromagnetic layer, while the lower conductor track, which forms the word line WL, is connected to the lower magnetized layer ML
2
, which may likewise be a ferromagnetic layer. If a voltage is applied to the memory cell via the two conductor tracks for the word line WL and the bit line BL, then a tunnel current flows through the thin nonmagnetized intermediate layer TL. The thin nonmagnetic intermediate layer then forms the resistance R
C
which, depending on the parallel or anti-parallel alignment of the magnetic moments, that is to say the parallel or anti-parallel polarization of the upper and lower ferromagnetic layer ML
1
and ML
2
, assumes the magnitude R
C
(“0”)<R
C
(“1”) or R
C
(“1”)=R
C
(“0”)+&Dgr;R
C
given a suitable voltage across the memory cell.
FIG. 6
shows a memory cell array, in which memory cells are disposed in the form of a matrix at crossing points between the word lines WL and the bit lines BL.
The cell contents are indicated schematically here for two memory cells as “1” and “0”, depending on the anti-parallel or parallel polarization.
In a memory cell array, such as is shown in
FIG. 6
, not only does a current then flow via the memory cell at the crossing point between a selected word line WL and a selected bit line BL, but undesired secondary currents also occur on further memory cells, which are in each case connected to the selected word line WL and the selected bit line BL. These undesired secondary currents interfere to a considerable extent with the read current that flows through the selected memory cell.
Attempts have therefore already been made to separate undesired secondary currents from the read current to a great extent, by suitable wiring of the memory cell array, so that only the read current through the selected memory cell or the read voltage across the memory cell is available for detection. In this case, however, the resistance value of the memory cells must be selected to be high and, in particular, in the MOhm range, because of the parasitic currents through the other memory cells, in order to be able to construct sufficiently large memory cell arrays.
Another way of avoiding the undesired secondary currents is to supplement an MTJ memory cell of intrinsically simple construction (see FIG.
7
A), by a diode D (see FIG.
7
B), or by a switching transistor T (see
FIG. 7C
) (see the references by R. Scheuerlein e.a., titled “A 10 ns Read and Write Time Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET-Switch in each Cell”, ISSCC February 2000 p. 128/and R. C. Sousa e.a., titled “Vertical Integration Of A Spin Dependent Tunnel Junction With An Amorphous Si Diode”, appl. Phys. Letter Vol. 74, No. 25, pp. 3893 to 3895).
The advantage of such supplementation by the diode D or the switching transistor T resides in the fact that, with such circuitry, in a memory cell array only a read current flows through the selected memory cell, since all the other memory cells are turned off. As a result, the resistance value of the memory cell can be selected to be lower, as opposed to a pure MTJ cell corresponding to
FIG. 7A
, as a result of which the read current becomes relatively high and reading can be carried out quickly in the ns range. However, the disadvantage of such additional circuitry with a diode or a transistor is the considerable additional expenditure on technology and area necessitated thereby.
In the case of the current prior art, the common factor in all memory cell types is that the detection or evaluation of a read signal as a “0” or “1” is very difficult, since the tunnel
Hoffmann Kurt
Kowarik Oskar
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
Nguyen Tan T.
Stemer Werner H.
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