Circuit for multiplying a pump clock voltage

Details Circuit for multiplying a pump clock voltage Circuit for multiplying a pump clock voltage

1985-04-30

1988-03-29

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307110, 307529, 307264, 328160, H03K 501, H03K 424

Patent

active

047345993

ABSTRACT:
A voltage multiplier circuit is disclosed. The circuit comprises three p-channel MOS transistors and three capacitors. When these elements are connected to properly phased transfer and pump clock signals of positive polarity, the circuit generates a negative output voltage which is roughly equal in magnitude to the peak-to-peak voltage of the pump clock. One of the transistors couples the output node to the circuit input node, and is clocked by the transfer clock so as to isolate the input node from the output node when the output node potential is lower than the input node potential. Several of the circuits may be cascaded to produce a large negative supply from a small positive supply. The circuit is advantageously employed to provide the programming signal supply for EEPROM devices.

REFERENCES:
patent: 3975671 (1976-08-01), Stoll
patent: 4382194 (1983-05-01), Nakano et al.
patent: 4398100 (1983-08-01), Tobita et al.
patent: 4485433 (1984-11-01), Topich

Affiliated with

Also associated with

Rating

Circuit for multiplying a pump clock voltage does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Circuit for multiplying a pump clock voltage, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit for multiplying a pump clock voltage will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1090481