Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Patent
1997-06-02
2000-02-22
Cabeca, John W.
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
711 2, 711167, 711169, G06F 1206, G06F 1314
Patent
active
060292334
ABSTRACT:
Electrical circuit (5) arranged to move data blocks from a source memory unit (8, 9, 12) to a target memory unit (9, 12, 8) by a data path (5, 6, 7), to send, in a given order, requests to read blocks in the source memory, to generate an end marker in the request to read the last block of the source memory, to receive the blocks read, in the form of response messages, in the order in which the requests were sent, and to send requests to write the received blocks, in the target memory, during receiving of response messages until receiving a message from the source memory with the end marker.
REFERENCES:
patent: 5432923 (1995-07-01), Taniguchi et al.
patent: 5469558 (1995-11-01), Lieberman et al.
patent: 5617529 (1997-04-01), Dao
patent: 5734857 (1998-03-01), Gaubatz
patent: 5761735 (1998-06-01), Huon et al.
Abily Jack
Autechaud Jean-Fran.cedilla.ois
Dionet Christophe
Bull S.A.
Cabeca John W.
Chow Christopher S.
Kondracki Edward J.
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