Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-08-09
2001-07-24
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S296000, C257S300000
Reexamination Certificate
active
06265737
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to integrator circuits for photogenerated charges. Its object is in particular to limit the linearity defects caused by stray capacitances.
2. Discussion of the Background
Such circuits have the function of converting into voltage a quantity of current or charges which are accumulated during an integration time. Such integrator circuits are commonly used in various fields, examples of which include detector panels for digitized images, in particular radiological digitized images.
Taking as an example detector panels for digitized images, these generally have a matrix of photosensitive points. Each photosensitive point delivers a quantity of charges proportional to the intensity of a light signal to which it has been exposed. For each photosensitive point, these photogenerated charges are converted into a voltage value which is subsequently read then stored to form an elementary point of a digital image.
The commonest process for carrying out this conversion into voltage consists in charging a capacitor, as shown in FIG.
1
.
FIG. 1
represents a conventional diagram of such an integrator circuit. The integrator circuit
1
has a so-called integration capacitor c
1
, one plate
2
of which is connected to a reference potential Vr: in the example represented, this reference potential consists of a supply potential V+ which is positive relative to the general earth of the circuit; the reference voltage may, however, be different, for example lying between the supply potential V+ and earth. The second plate
3
of the integration capacitor c
1
is connected to a point “A” where a conductor
4
carrying charges Q arrives. These charges, which are intended to be integrated by the integration capacitor c
1
, are delivered by a charge generator
5
, for example of the type consisting of a matrix of photosensitive points.
The point “A”, that is to say the second plate
3
of the integration capacitor c
1
, constitutes a point at variable potential: the voltage at point “A” varies relative to the reference potential V+, as a function of the quantity of charge accumulated by the integration capacitor c
1
, according to the equation: V=Q/c
1
where V is the increasing voltage, Q is the quantity of charges and c
1
is the integration capacitance.
The simplest way of producing a capacitor consists, for example, in forming it from the gate of a transistor of the MOS type (metal oxide semiconductor). However, capacitors of this type are nonlinear, and their value varies with this voltage applied to their terminals. Thus, in order to guarantee the linearity of the measurements, it is generally preferred to form an integration capacitor such as c
1
using a capacitor of the MIM type (metal insulator metal) which is independent of voltage.
The integration capacitor c
1
is called on to successively integrate the quantities of charges Q corresponding to different successive measurements; it is therefore necessary, before each measurement, to remove the charge stored by the integration capacitor in order to avoid voltage drifts, and to make it possible to start regularly from a stable and known value of the voltage across the terminals of the integration capacitor c
1
. This is accomplished by a so-called resetting operation, which consists in short-circuiting the integration capacitor c
1
using an element fulfilling a switch function.
In order to carry out this resetting operation, it is conventional to use a semiconductor device such as a transistor of the MOS type controlled in all or nothing mode, as represented in
FIG. 1
by a resetting transistor t
1
. Transistor t
1
is of the “P” channel MOS type, and its source S
1
is connected to the first plate
2
of the integration capacitor c
1
and therefore to the reference voltage V+. The drain D
1
of transistor t
1
is connected to the point “A” at variable potential, that is to say to the second plate
3
of the integration capacitor c
1
, and its gate G is connected to a resetting control circuit
6
from which it receives a resetting control signal.
One drawback of the conventional layout described above resides in the fact that, since the drain D
1
of the resetting transistor t
1
is connected to the second plate
2
, it brings in parallel with the integration capacitor c
1
a stray capacitance cp
1
(represented by dashes in
FIG. 1
) which is formed by a junction which this drain D
1
constitutes. By way of explanation, it is known that the drain D
1
, and also the source S
1
, of such a transistor t
1
each consist of a region which is implanted in a semiconductor substrate with which they each form a junction.
The drain and source each consist of a semiconducting region, doped with a conductivity type which is opposite to that of the substrate. Thus, for example, a P type or P channel transistor has an N doped substrate which is brought to the positive potential of the supply voltage applied to the circuit (as represented in
FIG. 1
where the substrate B
1
of transistor t
1
is connected to the positive potential V+); the drain and the source of this transistor are formed by “N” doped regions implanted in this substrate. An N type transistor is, conversely, referenced relative to a substrate which is at the negative potential of the supply voltage.
Under these conditions, the drain D
1
consists of a junction biased in the “off” direction, that is to say by a reversed-biased diode, which diode consequently constitutes a stray capacitance cp
1
arranged in parallel with the integration capacitor c
1
(as is represented by dashes in the figure).
Since the voltage across the terminals of the integration capacitor c
1
varies because of the integration of the charges and, furthermore, as already indicated above, the value of the stray capacitance cp
1
is strongly dependent on the voltage across these terminals, the resulting capacitance has a significant nonlinear component. This nonlinear part of the capacitance has of course an affect which is all the more marked as the capacitance of the integration capacitor c
1
is small.
It should be noted that the problem thus created by the presence of the switching element constituted by the transistor t
1
is all the more pronounced if an integrator with high sensitivity is desired, which sensitivity becomes higher as the integration capacitance becomes smaller.
In the case, for example, of an integrator circuit receiving charges produced by a photosensitive matrix, it is common for the integration capacitor to have a capacitance of the order of 0.3 to 0.5 pF. The nonlinearity generated just by the stray capacitance, that is to say by the presence of the switch constituted by the transistor t
1
, may reach 1%, and even extend to 5%, in the case of an operating voltage range corresponding to a voltage variation of the order of 3 volts.
With the aim of reducing the effect of the stray capacitance cp
1
, one solution consists in using, as the switch, MOS transistors having a small junction area. However, the limits of this solution are rapidly reached without really providing satisfaction, because the constituent elements of these transistors cannot be made small enough for technologically related reasons.
SUMMARY OF THE INVENTION
With a view to reducing, or even eliminating, from an integration circuit the detrimental effects of a stray capacitance consisting of a semiconductor junction provided, in particular, by a transistor as explained above, the invention proposes to compensate for the different variations caused by this stray capacitance, by variations which are made in an opposite direction and are caused by at least one other semiconductor junction.
The invention proposes an integrator circuit for photogenerated charges, having an integration capacitor of which a first plate is connected to a reference potential and a second plate to a point at variable potential where it receives the photogenerated charges, a resetting MOS transistor of a first type, connected on the one hand t
Ngo Ngan V.
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Thomson Tubes Electroniques
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