Circuit for inhibition of program disturbance in memory devices

Details Circuit for inhibition of program disturbance in memory devices Circuit for inhibition of program disturbance in memory devices

2007-05-08

2007-05-08

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

C365S185210

Reexamination Certificate

active

11204477

ABSTRACT:
A method and system is disclosed for prohibiting program disturbance in a memory array device. The system comprises a bit-line decoder coupled to each bit-line of the memory array for providing a predetermined current diverting path, a biased resistance module placed on the bit-line of the flash memory array through which a pull-up current provided by a predetermined power supply is diverted by the bit-line decoder when a cell of the flash memory array connecting to the bit-line is programmed. The programming current of the cell of the flash memory array is stabilized due to the diverted pull-up current.

REFERENCES:
patent: 5995423 (1999-11-01), Lakhani et al.
patent: 6128221 (2000-10-01), Chih
patent: 7110308 (2006-09-01), Wang
patent: 2004/0218422 (2004-11-01), Nguyen et al.

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