Circuit for improving noise immunity by DV/DT boosting

Details Circuit for improving noise immunity by DV/DT boosting Circuit for improving noise immunity by DV/DT boosting

2002-06-28

2003-08-26

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C326S031000

Reexamination Certificate

active

06611154

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a level shift circuit for high frequency level shift operation and, more specifically, to a circuit which provides immunity against common mode variations for high frequency level shift operations.
2. Description of the Related Art
Level shift circuits for shifting the potential of a small control signal to a higher or a lower voltage level are well known, and are frequently implemented into power integrated circuit chips. A typical power integrated circuit chip is the IR2151 sold by the International Rectifier Corporation, the assignee of the present invention. The IR2151 is a high voltage, high speed MOS gated IC with independent high side and low side outputs for driving the gates of high side and low side power transistors (typically power MOSFETs or insulated gate bipolar transistors (“IGBTs”)) arranged in a half-bridge configuration. The level shift circuit is used in such power integrated circuits for raising the voltage level of the control signal for the high side power transistor to a level near the level of the high voltage rail.
Level shift circuits such as the one used in the IR2151 power IC are typically pulse-based circuits in which the input control signal is converted into pulses at the rising and falling edges of the control signal to provide “set” and “reset” for a latch which in turn controls the gate of the high side power transistor. By level shifting these pulses, instead of the control signal, the level shift circuit is turned on only briefly, thereby dissipating much less power.
U.S. Pat. No. 5,514,981, assigned to the assignee of the present invention and incorporated herein by reference, discloses a “reset dominant” scheme for a pulse-based level shift circuit which prevents false operation, i.e., the production of an output which is not called for by the logic input, as a result of a noise “glitch” or false pulse.
FIG. 1
of the present application shows the pulse-based level shift circuit of U.S. Pat. No. 5,514,981, in which rising and falling edges of an input signal cause a pulse generator
1
to produce set and reset pulses which are fed to respective high voltage level transistors
2
,
3
, which, after passing through pulse filter block
9
, respectively set and reset an RS latch
4
. The output
5
of RS latch
4
, which constitutes the high voltage equivalent of the low voltage control signal, and is used to control the switching of output transistors
6
,
7
which in turn produce a signal at an intermediate pin HO which is used to gate the high side power transistor connected to the IC.
One problem associated with pulse-based level shift circuits such as those shown in
FIG. 1
is that the pulses are of a constant width and amplitude, which affects both propagation delay from input to output and also power dissipation, potentially limiting frequency of operation.
To overcome the above-noted limitation, an alternative level shift circuit has been proposed, which is disclosed and claimed in U.S. Ser. No. 09/984,084, filed Oct. 26, 2001 (IR-1934), which does not operate on pulses generated from the input signal, and is thus not constrained by pulse characteristics. Referring to
FIG. 2
, this non-pulse level shift circuit includes switching circuitry (namely, transistors
20
and
22
and inverter
24
), which responds to transitions between high and low values in the input signal, turning a first current path on in response to a low-to-high transition in the input signal V
IN
, and turning a second current path on in response to a high-to-low transition in the input signal. This is accomplished by driving the gates of transistors
20
and
22
with two anti-phase signals: transistor
20
receives IN, which is the input signal from source V
IN
without inversion; transistor
22
receives IN*, which is an inverted version of input signal V
IN
produced by inverter
24
.
The shifting circuitry of the non-pulse level shift circuit shown in
FIG. 2
is formed of enhancement-mode transistors
30
and
32
and provides output signals OUT and OUT* at nodes
34
and
36
. The shifting circuitry responds to the current flowing in the first and second paths, thereby shifting the level of the output signals (OUT or OUT*) according to a transition in the input signal and turning off the path that was turned on by the switching circuitry.
The parasitic capacitance associated with transistors
2
,
3
in the prior art level shift circuit of
FIG. 1
, and with transistors
20
and
22
in the non-pulse based level shift circuit of
FIG. 2
, are primarily associated with the dv/dt problem. When a dv/dt occurs on the Vs node, false operation of the IC can occur unless sufficient current is supplied to charge these parasitic capacitances.
By implementing the circuit of the present invention, the need for a pulse filter block
9
is reduced or eliminated, which in turn reduces the propagation delay of the IC.
SUMMARY OF THE INVENTION
The circuit of the present invention advantageously overcomes the above-noted deficiencies of the prior art by sensing the amount of current that must be supplied to the parasitic capacitors associated with the level shift transistors during a dv/dt condition, and injecting this current in a timely manner to prevent false operation of the IC.
Other features and advantages of the present invention will become apparent from the following description of the invention which refers to the accompanying drawings.


REFERENCES:
patent: 5001369 (1991-03-01), Lee
patent: 5933021 (1999-08-01), Mohd
patent: 5955911 (1999-09-01), Drost et al.
patent: 6184701 (2001-02-01), Kim et al.
patent: 6281706 (2001-08-01), Wert et al.
patent: 05283944 (1993-10-01), None

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