Circuit for implementing special mode in packet-based...

Details Circuit for implementing special mode in packet-based... Circuit for implementing special mode in packet-based...

2006-06-06

2006-06-06

Sparks, Donald (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S005000, C711S211000, C365S189050

Reexamination Certificate

active

07058756

ABSTRACT:
Disclosed is a circuit for implementing a special mode in a packet-based semiconductor memory device, which performs the special mode in the same manner as a normal operation without changing the semiconductor memory devie from a special mode register to a control register mode prior to a normal operation or at the middle of the normal operation after an initial operation having a reset operation. A packet receiving part receives external packet data. A register controller generates a control signal to select a special mode register according to a value of a first field among the external packet data received by the packet receiving part. A register value generator generates a value of the special mode register selected by the control signal from the register controller according to a value of a second field among the received external packet data when the register controller generates the control signal.

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patent: 6633947 (2003-10-01), Holman et al.
patent: 6766383 (2004-07-01), Pan et al.

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