Electronic digital logic circuitry – Function of and – or – nand – nor – or not – Field-effect transistor
Reexamination Certificate
2000-06-28
2004-09-14
Cho, James H. (Department: 2819)
Electronic digital logic circuitry
Function of and, or, nand, nor, or not
Field-effect transistor
C326S047000
Reexamination Certificate
active
06791366
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method and/or architecture for input circuits generally and, more particularly, to a method and/or architecture for implementing a circuit for product term inputs.
BACKGROUND OF THE INVENTION
A programmable logic device (PLD) provides an economical and efficient means for implementing predetermined Boolean logic functions in an integrated circuit. Such a device consists of, generally, an AND plane configured to generate predetermined product terms in response to a plurality of inputs, a group of fixed/programmable OR gates configured to generate a plurality of sum-of-product(SOP) terms in response to the product terms, and a number of logic elements (i.e., macrocells) configured to generate a desired output in response to the sum-of-products terms. The sum-of-products terms can also be generated using programmable NOR-NOR logic.
The arrangement and operation of components within the PLD are programmed by architecture configuration bits. The architecture configuration bits are set prior to normal operation of the PLD. The configuration bits can be stored in volatile memory (i.e., SRAM) or non-volatile memory (i.e., EEPROM/flash). The bits are set using an operation called “programming” or “configuration”.
Depending upon the Boolean function implemented, the plurality of inputs to the AND plane of the PLD can require a number of input signals, digital complements of the input signals, and logic levels (i.e., “0” or “1”). The plurality of inputs are presented by product term input circuits. In order to maximize the number of input signals to a PLD (i.e., avoid sacrificing an input to generate a logic level), the product term input circuits need to be able to select either an input signal, a complement of the input signal, or a logic level.
Referring to
FIG. 1
, a schematic-diagram of a circuit
20
illustrating a conventional polarity switch is shown. The circuit
20
has an inverter
22
, a PMOS transistor
24
, a NMOS transistor
26
, a PMOS transistor
28
, a NMOS transistor
30
, and an inverter
32
. The transistors
24
and
26
form a first transmission gate and the transistors
26
and
28
form a second transmission gate. An enable signal EN is presented to an input of an inverter
34
via a pad
36
. An output of the inverter
34
presents a signal to an input of the inverter
22
, a gate of the transistor
24
, and a gate of the transistor
30
. An output of the inverter
22
presents a signal to a gate of the transistor
26
and a gate of the transistor
28
. An input signal IN is presented to an input of the inverter
32
and a first source/drain of the transistors
28
and
30
. An output of the inverter
32
is presented to a first source/drain of the transistors
24
and
26
. A second source/drain of the transistors
24
,
26
,
28
, and
30
are connected to form a node at which an output signal OUT is presented. Depending upon the state of the enable signal EN, either the signal IN or a complement of the signal IN will be presented as the signal OUT.
Referring to
FIG. 2
, a schematic diagram of a circuit
36
illustrating a memory cell generating the enable signal EN of
FIG. 2
is shown. The circuit
36
comprises a non-volatile memory cell
38
and a driver circuit
40
. An output of the memory cell is presented to an input of the driver circuit
40
. The driver circuit
40
comprises an inverter
42
, a transistor
44
, a transistor
46
and a transistor
48
. The signal from the memory cell
38
is presented to an input of the inverter
42
, a gate of the transistor
46
and a gate and source of the transistor
48
. An output of the inverter
42
presents the signal EN to the circuit
20
and a gate of the transistor
44
. A source of the transistor
44
is connected to a source of the transistor
46
and a supply voltage VCC. A drain of the transistors
44
,
46
, and
48
are connected together.
The circuit
20
can present only the signal IN or a complement of the signal IN. The circuit
20
requires eight transistors. In order to select between the signal IN, a complement of the signal IN, and a logic level, a product term input circuit would require two of the circuits
20
. The product term input circuits account for a significant portion of the transistors in a PLD. Doubling the number of transistors needed for a product term input circuit with redundant logic is undesirable. Since the product term input circuits account for a significant portion of the transistors in a PLD, a product term input circuit that could select between signal polarities and logic levels with fewer transistors would be desirable.
SUMMARY OF THE INVENTION
The present invention concerns an apparatus comprising a polarity switch. The polarity switch may comprise a number of transmission gates. An output of the polarity switch may selectably present either (i) a signal that varies in response to a control signal or (ii) a predetermined logic level that is independent of the control signal.
The objects, features and advantages of the present invention include providing a method and/or architecture for implementing a product term input circuit that may (i) be implemented in a complex programmable logic device (CPLD), (ii) provide a reduction in the number of transistors needed for implementing product term inputs, (iii) provide a reduction in area for implementing the same number of product term inputs, (iv) provide the capability to implement a larger number of product term inputs in a given area and/or (v) provide a reduction in interconnect length and/or a reduction in delay on a CPLD.
REFERENCES:
patent: 4879688 (1989-11-01), Turner et al.
patent: 4992679 (1991-02-01), Takata et al.
patent: 5233233 (1993-08-01), Inoue et al.
patent: 5412599 (1995-05-01), Daniele et al.
patent: 5687107 (1997-11-01), Igura
patent: 5889413 (1999-03-01), Bauer
patent: 5952846 (1999-09-01), Silver
patent: 6194914 (2001-02-01), Sako
patent: 6359466 (2002-03-01), Sharpe-Geisler
patent: 61173518 (1986-08-01), None
Cho James H.
Christopher P. Maiorana P.C.
Cypress Semiconductor Corp.
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