Circuit for glitchless switching between asynchronous clocks

Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates

Reexamination Certificate

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Details

C326S016000, C327S298000

Reexamination Certificate

active

07944241

ABSTRACT:
A circuit for glitchless switching between asynchronous clocks includes a select circuit and enable circuits. The select circuit receives a selection signal for selecting one of the clock input signals and to generate enabling signals for activating the corresponding enable circuits on the basis of the current output signal. The feedback logic in the circuit ensures that at any given instance only one of the clock input signals is outputted so as to avoid the formation of glitches. The circuit can be applied to switches between any number of asynchronous clocks.

REFERENCES:
patent: 5155380 (1992-10-01), Hwang et al.
patent: 5315181 (1994-05-01), Schowe
patent: 5623223 (1997-04-01), Pasqualini
patent: 6265930 (2001-07-01), Walker et al.
patent: 6266780 (2001-07-01), Grundvig et al.
patent: 6275546 (2001-08-01), Miller et al.
patent: 6577169 (2003-06-01), Cheng
patent: 6593780 (2003-07-01), Lammers
patent: 63259711 (1988-10-01), None

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