Static information storage and retrieval – Systems using particular element – Ferroelectric
Reexamination Certificate
2001-11-16
2002-12-24
Elms, Richard (Department: 2824)
Static information storage and retrieval
Systems using particular element
Ferroelectric
C365S185200, C365S185210
Reexamination Certificate
active
06498745
ABSTRACT:
This application claims the benefit of Korean Application No. P2000-68112 filed on Nov. 16, 2000, which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a circuit for generating timing of a reference plate line in a nonvolatile ferroelectric memory device and a method for driving a reference cell. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for improving a sensing margin by stabilizing a reference level in the nonvolatile ferroelectric memory device.
2. Discussion of the Related Art
Generally, a nonvolatile ferroelectric memory, i.e., a ferroelectric random access memory (FRAM), has a data processing speed equal to a dynamic random access memory (DRAM) and is able to retain data even in power off. For this reason, the nonvolatile ferroelectric memory has received much attention as a next generation memory device.
The FRAM and DRAM are memory devices having a similar structure, but the FRAM includes a ferroelectric capacitor having a high residual polarization characteristic.
The residual polarization characteristic permits data to be maintained even if an electric field is removed.
FIG. 1
shows a hysteresis loop of a typical ferroelectric.
As shown in
FIG. 1
, even if the electric field is removed from the polarization induced by the electric field, data is maintained at a certain amount (i.e., ‘d’ and ‘a’ states) due to a residual polarization (or spontaneous polarization).
A nonvolatile ferroelectric memory cell is used as a memory device by corresponding the ‘d’ and ‘a’ states to ‘
1
’ and ‘
0
’, respectively.
However, a related art ferroelectric hysteresis loop according to the related art reference cell operation has problems deviated from the hysteresis characteristics of the typical ferroelectric.
For a better understanding of the background technology, a cell array block, a main cell, and a reference cell of the nonvolatile ferroelectric memory device to apply a driving method of a reference cell will be explained hereinafter.
FIG. 2
shows a schematic diagram of a cell array block according to a nonvolatile ferroelectric memory device applicable to a driving method of a reference cell.
FIG. 3
is a schematic diagram of a main cell of
FIG. 2
, while
FIG. 4
is a detailed circuit diagram of a reference cell of FIG.
2
.
The cell array block includes a plurality of sub cell arrays. A sensing amplifier S/A is formed between adjacent top and bottom sub cell arrays sub_T and sub_B.
Each of the sub cell arrays includes bit lines Top_B/L and Bot_B/L, a plurality of main cells MC connected to the bit lines Top_B/L and Bot B/L, a reference cell RC connected to the bit lines Top B/L and Bot_B/L, and a column selector CS.
The reference cell RC within the top sub cell array sub_T S/A is simultaneously accessed when the main cell MC within the bottom sub cell array sub_B is accessed.
Similarly, the reference cell RC within the bottom sub cell array sub_B is simultaneously accessed when the main cell MC within the top sub cell array sub_T is accessed.
The column selector CS selectively activates a corresponding column bit line using Y (column) address.
If the column selector CS is in high level, the corresponding bit line is connected to a data bus, so as to enable a data transmission.
The main cell MC is constructed as shown in
FIG. 3. A
bit line B/L is formed in one direction, and a wordline W/L is formed to cross the bit line B/L. A plate line P/L is spaced apart from the wordline W/L in the same direction as the wordline W/L. A transistor T is formed with a gate connected to the wordline W/L and a source connected to the bit line B/L. A ferroelectric capacitor FC is formed in such a manner that a first terminal is connected to a drain of the transistor T and a second terminal is connected to the plate line
2
/L.
The respective reference cell is constructed as shown in FIG.
4
.
As shown in
FIG. 4
, the reference cell of the nonvolatile ferroelectric memory device includes a bit line B/L formed in one direction, a reference wordline REF_W/L formed across the bit line B/L, a switching block
51
, a level initiating block
52
, and a plurality of ferroelectric capacitors FC
1
, FC
2
, FC
3
, FC
4
, . . . , and FCn. The switching block
51
is controlled by a signal of the reference wordline REF W/L to selectively transmit a reference voltage stored in the ferroelectric capacitors to the bit line B/L. The level initiating block
52
selectively initiates a level of an input terminal of the switching block
51
connected to the ferroelectric capacitors. The ferroelectric capacitors are connected to the input terminal of the switching block
51
in parallel.
The switching block
51
includes an NMOS transistor (hereinafter, “first transistor”) T
1
with a gate connected to the reference wordline REF_W/L, a drain connected to the bit line B/L, and a source connected to a storage node SN.
The level initiating block
52
is controlled by a reference cell equalizer control signal REF_EQ which is a control signal for initiating the storage node SN of the reference cell. Also, the level initiating block
52
includes an NMOS transistor (hereinafter, “second transistor”) T
2
connected between the source of the first transistor T
1
and a ground terminal Vss.
The plurality of ferroelectric capacitors FC
1
, FC
2
, FC
3
, FC
4
, . . . , and FCn include first and second electrodes, and a ferroelectric material formed between them. The first electrode of the ferroelectric capacitors is connected to the source of the first transistor T
1
, and the second electrode is connected to the reference plate line REF_P/L.
Herein, the number of the ferroelectric capacitors FC
1
, FC
2
, FC
3
, FC
4
, . . . , and FCn is determined by the capacitor size of the reference cell. Thus, the number of the ferroelectric capacitors can freely be adjusted by changing the capacitor size of the reference cell.
The storage node SN is connected with first terminals of the ferroelectric capacitors FC
1
, FC
2
, FC
3
, FC
4
, . . . , and FCn in parallel.
The reference cell equalizer control signal REF_EQ initiates the storage node SN to a ground voltage level. Namely, if the reference cell equalizer control signal REF_EQ is in high level, the second transistor T
2
is turned on so that the storage node is maintained at a ground voltage level.
Operation of the aforementioned reference cell will now be described.
Qs and Qns of hysteresis loop in
FIG. 1
denote switching charges of the ferroelectric capacitor, and non-switching charges of the ferroelectric capacitor, respectively. The reference cell of the present invention is based on Qns.
That is, the reference wordline REF_W/L within the operation cycle is transited to high level together with the reference plate line REF_P/L. Accordingly, charges equivalent to Qns X the size of ferroelectric capacitor are supplied to the bit line B/L.
At this time, the reference wordline REF_W/L is transited to low level before the sensing amplifier S/A is operated, so that the reference cell is not affected by a voltage of the bit line B/L.
Meanwhile, the reference plate line REF_P/L is maintained at high level, and transited to low level when the reference wordline REF_W/L is sufficiently stabilized to low level.
Since non-switching charges Qns are used, a separate restoring operation is not required during a precharge period. Accordingly, high level is no longer required in the reference wordline REF_W/L.
Since the reference level is affected by an initial level of the storage node, the second transistor T
2
of
FIG. 4
is used to stabilize the storage node, and the reference equalizer control signal REF_EQ is used to initiate the storage node to the ground voltage level.
Therefore, since the initial level of the storage node is maintained at the ground voltage level, the reference level can be stabilized.
Hereinafter, a hysteresis characteristic of the related art ferroelectric and a
Kang Hee Bok
Kye Hun Woo
Park Je Hoon
Elms Richard
Hynix / Semiconductor Inc.
Morgan & Lewis & Bockius, LLP
Nguyen Hien
LandOfFree
Circuit for generating timing of reference plate line in... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Circuit for generating timing of reference plate line in..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit for generating timing of reference plate line in... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2984139