Circuit for generating silicon ID for PLDS

Details Circuit for generating silicon ID for PLDS Circuit for generating silicon ID for PLDS

2005-07-26

2005-07-26

Whitmore, Stacy A. (Department: 2812)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C714S733000

Reexamination Certificate

active

06922820

ABSTRACT:
An apparatus comprising a circuit configured to select one of a number of identification (ID) codes in response to a voltage level at one or more pins.

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“IEEE Standard Test Access Port and Boundary-Scan Architecture, IEEE Std 1149.1-1990”. p. 1-127.
“Supplement to IEEE Std 1149.1-1990, IEEE Standard Test Access Port and Boundary-Scan Architecture”. p. 1-68.
IBM TDB Publication, “Using a portion of the boundary register as the identification register”, Sep. 1989, IBM vol. 32-4a. pp. 262-264.
“IEEE Standard Test Access Port and Boundary-Scan Architecture”, IEEE Std 1149.1-1990, pp. 1-127.
“Supplement to IEEE Std 1149.1-1990, IEEE Standard Test Access Port and Boundary-Scan Architecture”, IEEE Std 1149.1b-1994, pp. 1-68.
Zhiwu Liu, “Soft Coding of Multiple Device IDS for IEEE Compliant JTAG Devices”, U.S. Appl. No. 09/589,919, filed Jun. 7, 2000.

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