Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator
Reexamination Certificate
2001-12-28
2003-12-02
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
Including reference or bias voltage generator
C365S226000, C327S540000
Reexamination Certificate
active
06657903
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a circuit for generating a power-up signal in a semiconductor memory device, and in particular to an improved circuit for generating a power-up signal which can stabilize a power-up operation by generating the power-up signal by detecting a back bias voltage and an external power voltage in order to prevent a latch-up from being generated due to increase of the back bias voltage by coupling of the source, drain and gate voltages of a memory cell transistor in an initial power-up operation.
2. Description of the Background Art
FIG. 1
is a circuit diagram illustrating a conventional circuit for generating a power-up signal. Referring to
FIG. 1
, in the circuit for generating the power-up signal, a resistor R and a capacitor C are connected in series between a power voltage VCC and a ground voltage VSS. When the power voltage VCC is applied, a voltage divided by the RC time constant of the resistor R and the capacitor C is charged through a node Nd
1
.
In addition, inverters IV
1
and IV
2
are connected in series between the node Nd
1
and an output terminal. When the voltage of the node Nd
1
is greater than a logic threshold voltage Vt of the inverter IV
1
, a power-up bar signal PUPB outputted to the output terminal has a low level.
On the other hand, internal circuits of a semiconductor memory device are not operated in a power-up operation. Here, the circuit for generating the power-up signal initializes the internal circuits that are to be stabilized.
However, the conventional circuit generates the power-up signal PUPB through an RC delay, and thus a considerable level difference is created in response to a power-up sequence. Therefore, when the external power voltage is low, the internal circuits are not successfully initialized, which may generate a current path. In addition, when the power-up operation is performed with an unstable back bias voltage, the back bias voltage is increased due to coupling of the source, drain and gate voltages of a memory cell transistor, thereby generating a latch-up.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a circuit for generating a power-up signal in a semiconductor memory device which can remove instability due to non-generation of a back bias voltage by detecting the back bias voltage of a memory cell internally generated when an external power voltage is applied, and detecting the external power voltage when the back bias voltage reaches a predetermined level, and which can improve stability of the power-up signal by initializing an external power voltage detecting unit by using an initial start-up circuit.
In order to achieve the above-described object of the invention, there is provided a circuit for generating a power-up signal in a semiconductor memory device including: a VBB level detecting unit for detecting a back bias voltage level; an external power voltage detecting unit controlled in response to the signal from the VBB level detecting unit, for detecting an external power voltage level; a start-up circuit unit for setting an initial value of the external power voltage detecting unit; an output unit controlled in response to the output signal from the VBB level detecting unit, for buffering and outputting the signal from the external power voltage detecting unit; and a connection unit for receiving the signal from the output unit, and controlling source, drain and gate voltages of a memory cell transistor.
In another aspect of the present invention, a circuit for generating a power-up signal in a semiconductor memory device includes: a VBB level detecting unit for detecting a back bias voltage level; an external power voltage detecting unit controlled in response to the signal from the VBB level detecting unit, for detecting an external power voltage level; a start-up circuit unit for setting an initial value of the external power voltage detecting unit; an output unit for buffering the signal from the external power voltage detecting unit; and a connection unit for receiving the signal from the output unit, and controlling source, drain and gate voltages of a memory cell transistor.
In still another aspect of the present invention, a circuit for generating a power-up signal in a semiconductor memory device includes: an external power voltage detecting unit for detecting an external power voltage in response to the active resistance ratio of a transistor; a start-up circuit unit for setting an initial value of the external power voltage detecting unit; an output unit for buffering the signal from the external power voltage detecting unit; and a connection unit for receiving the signal from the output unit, and controlling the source, drain and gate voltages of a memory cell transistor.
In still another aspect of the present invention, a circuit for generating a power-up signal in a semiconductor memory device includes: an external power voltage detecting unit for detecting an external power voltage in response to the active resistance ratio of a transistor; a start-up circuit unit for setting up an initial value of the external power voltage detecting unit; an output unit controlled in response to the output signal from the start-up circuit unit, for buffering the signal from the external power voltage detecting unit; and a connection unit for receiving the signal from the output unit, and controlling the source, drain and gate voltages of a memory cell transistor.
In still another aspect of the present invention, a circuit for generating a power-up signal in a semiconductor memory device includes: an internal power voltage detecting unit for detecting an internal power voltage level; an external voltage detecting unit controlled in response to the signal from the internal power voltage detecting unit, for detecting an external voltage level; a start-up circuit unit for setting an initial value of the external power detecting unit; an output unit controlled in response to the signal from the internal power voltage detecting unit, for buffering the signal from the external power detecting unit; and a connection unit for receiving the signal from the output unit, and controlling the source, drain and gate voltages of a memory cell transistor.
In still another aspect of the present invention, a circuit for generating a power-up signal in a semiconductor memory device includes: an internal power voltage detecting unit for detecting an internal power voltage level; an external power detecting unit controlled in response to the signal from the internal power voltage detecting unit, for detecting an external voltage level; a start-up circuit unit for setting up an initial value of the external power detecting unit; an output unit for buffering the signal from the external power detecting unit; and a connection unit for receiving the signal from the output unit, and controlling source, drain and gate voltages of a memory cell transistor.
REFERENCES:
patent: 5920208 (1999-07-01), Park
patent: 6097659 (2000-08-01), Kang
patent: 6147925 (2000-11-01), Tomishima et al.
patent: 6184730 (2001-02-01), Kwong et al.
patent: 6198344 (2001-03-01), Sung
patent: 6205079 (2001-03-01), Namekawa
patent: 6512398 (2003-01-01), Sonoyama et al.
patent: 11-203869 (1999-07-01), None
patent: 11-260064 (1999-09-01), None
Elms Richard
Hynix / Semiconductor Inc.
Jacobson & Holman PLLC
Nguyen Nam
LandOfFree
Circuit for generating power-up signal does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Circuit for generating power-up signal, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit for generating power-up signal will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3180402