Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2000-06-28
2001-10-30
Nelms, David (Department: 2818)
Static information storage and retrieval
Addressing
Sync/clocking
C365S193000, C365S230060
Reexamination Certificate
active
06310823
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a synchronous semiconductor memory device, and more particularly to a synchronous semiconductor memory device for accurately interrupting an internal column strobe signal corresponding to an input command in a high and a low frequencies, when interrupt commands such as read and burst stop commands are received in the middle of a burst length set in a mode set register MRS in operation of the synchronous semiconductor memory device.
2. Description of the Related Art
FIG. 1
shows a block diagram of a synchronous semiconductor memory device which generates an internal column strobe signal in the prior art. The synchronous semiconductor memory device includes a clock buffer circuit
10
, an internal clock generation circuit
20
, a command decoder circuit
30
, a burst generation control circuit
40
, a burst signal generation circuit
50
and an internal column strobe generation circuit
60
. The clock buffer circuit
10
receives a clock enable signal cke and an external clock signal clk to generate an internal clock signal clkp
2
z. The internal clock generation circuit
20
receives the internal clock signal clkp
2
z generated from the clock buffer circuit
10
to generate another internal clock signal clkp
4
z.
The command decoder circuit
30
receives the internal clock signal clkp
4
z from the internal clock generation circuit
20
and external column strobe signals such as a chip select bar signal csb, a RAS (Row Address Strobe) bar signal rasb, a CAS (Column Address Strobe) bar signal casb, and a write enable bar signal web to generate internal command signals caspz, pcgpz and bstmpz.
The burst generation control circuit
40
receives input signals refx, cast
10
z<
0
:
3
>, eatz<
10
> and eatz<
13
:
14
> and the internal command signals pcgpz and bstmpz from the command decoder circuit
30
to generate a burst generation control signal bstm
10
pz. Herein, the input signal refx is a signal which is in a low state, only when the synchronous DRAM (SDRAM) is a refresh mode.
The burst signal generation circuit
50
receives a power-up signal pwrupz, the internal command signal caspz, the burst generation control signal bstm
10
pz, the input signal refx and a burst length stop signal yblendzp to generate a burst signal ybstz. Herein, the burst length stop signal yblendzp becomes disabled in a low state, when the burst length is stopped.
The internal column strobe generation circuit
60
receives the internal clock signal clkp
4
z and the burst signal ybstz to generate an internal column strobe signal icaspz.
FIG. 2
is a circuit diagram of the internal column strobe generation circuit
60
. As shown in
FIG. 2
, the internal column strobe generation circuit
60
includes a NAND gate ND
1
for receiving the internal clock signal clkp
4
z and the burst signal ybstz, inverters IN
1
and IV
2
connected in series between an output of the NAND gate ND
1
and a node Nd
1
, inverters IV
3
and IV
4
connected in series between the node Nd
1
and a node Nd
2
, a NAND gate ND
2
for receiving output signals of the inverters IN
2
and IV
4
at the nodes Nd
1
and Nd
2
and inverters IN
5
and IV
6
connected in series to an output of the NAND gate ND
2
and for generating the internal column strobe signal icasp
6
z.
The operation of the internal strobe generation circuit
60
will be described with reference to the timing diagram of FIG.
3
. First, the internal clock signal clkp
4
z of high state is generated with synchronization to the external clock signal clk, the command decoder circuit
30
receives the external command signals csb, rasb, casb, web) and the internal clock signal clkp
4
z and generates the external column strobe signal caspz by the internal clock signal clkp
4
z. After the external column strobe signal caspz is enabled, the burst signal generation circuit
50
which receives the external column strobe signal caspz generates the burst signal ybstz of high state.
The internal column strobe generation circuit
60
which receives the burst signal ybstz and the internal clock signal clkp
4
z generates the internal column strobe signal icasp
6
z with synchronization to the internal clock signal clkp
4
z during the enable interval of the burst signal ybstz, i.e. the high state of the burst signal ybstz.
However, the prior synchronous DRAM including the internal column strobe generation circuit
60
having the above construction immediately interrupts the internal column strobe generation circuit to generate the internal column strobe signal which is corresponding to the input command in a low frequency, if the interrupt commands such as read, write and burst stop commands are received in the middle of the burst length set through the mode register set MRS in operation of the SDRAM. Therefore, the time that the burst signal ybstz becomes in a low state in high frequency is slow so that the internal column strobe signal is generated after the burst stop.
FIG. 4
is a timing diagram illustrating the above problem. Referring to
FIG. 4
, it is noted that the internal column strobe signal icasp
6
z is also generated after the burst stop in high frequency. From the timing diagram of
FIG. 4
, because the signal indicating the burst length stop is disabled in a low state and then the burst signal ybstz is disabled after the lapse of a constant time, the internal column strobe signal icasp
6
z of one clock is generated, after burst stop. Accordingly, the undesired internal column strobe signal icasp
6
z causes the malfunction of the SDRAM, thereby occurring the current consumption.
Besides, in the prior SDRAM, only the burst signal ybstz interrupts the internal column strobe signal icasp
6
z. According to this, the construction of the burst signal generation circuit which generate the burst signal in accordance with the interrupt commands becomes complicate and it is difficult to control the operation of the SDRAM with the interrupt command.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a synchronous semiconductor memory device for accurately interrupting an internal column strobe signal in a high and a low frequencies, when interrupt commands such as read, write and burst stop commands are received in the middle of a burst length set in a mode set register in operation of the synchronous semiconductor memory device.
According to an aspect of the present invention, there is provided to a synchronous semiconductor memory device, comprising: burst signal generation means for generating a burst signal for controlling generation of an internal column strobe signal; burst generation control means for controlling generation of the burst signal; burst length stop signal generation means for generating a burst length stop signal for controlling a length of the burst signal to the burst signal generation means; and internal column strobe generation means for directly receiving output signals of a buffer command which are not decoded to generate an interrupt in the middle of the burst signal and generating the internal column strobe signal by the burst signal.
In the synchronous semiconductor memory, the internal column strobe generation mean includes: a decoder stage for receiving the output signals from the command buffer to generate a decoded signal; a stabilization stage for delay for a constant time and latching the decoded signal from the decoder stage; a logic operation stage for carrying out a logic operation of the burst signal and an internal clock signal; and an output stage for carrying out a logic operation of output signals from the decoder stage, the stabilization stage and the logic operation stage to generate the internal column strobe signal.
The output signals of the command buffer is a chip select signal, a RAS bar signal, a CAS bar signal and a write enable bar signal.
In the synchronous semiconductor memory device, the stabilization stage includes: a latch for latching the output signal of the decoder stage; and inverters connected in seri
Auduong Gene N.
Hyundai Electronics Industries Co,. Ltd.
Nelms David
Pillsbury & Winthrop LLP
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