Circuit for generating internal column address suitable for burs

Details Circuit for generating internal column address suitable for burs Circuit for generating internal column address suitable for burs

1996-12-19

1998-10-13

Nelms, David C.

Static information storage and retrieval

Addressing

Sync/clocking

36523008, 365236, G11C 800

Patent

active

058222707

ABSTRACT:
An internal column address generation circuit generates an internal column address by utilizing an asynchronous counter. The circuit includes a column address buffer for synchronizing an initially received external address with an external system clock to generate the internal column address, and for synchronizing a counting bit output signal received at an internal input node with the external system clock to generate the internal column address; and an asynchronous counter connected to an output node of the column address buffer, for generating the bit output signal having the same or opposite phase as/to a phase of the internal column address received from the column address buffer, in response to a carry generation state.

REFERENCES:
patent: 5513139 (1996-04-01), Butler
patent: 5539696 (1996-07-01), Patel
patent: 5566124 (1996-10-01), Fudeyasu et al.
patent: 5610874 (1997-03-01), Park et al.

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