Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2002-05-24
2004-10-26
Tra, Quan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
Reexamination Certificate
active
06809573
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a circuit for generating a high voltage, and more particularly, to a circuit for generating a high voltage in a semiconductor memory.
BACKGROUND OF THE INVENTION
FIG. 1
illustrates a circuit for generating a high voltage according to a related art disclosed in U.S. Pat. No. 5,276,646, incorporated herein by reference.
Referring to
FIG. 1
, a high voltage generating circuit according to the prior art includes pull-up transistors
11
and
12
of which gates and drains are connected to a power source voltage Vcc and a plurality of charge pumps
100
connected in series between sources of the pull-up transistors
11
and
12
. In this case, each of the charge pumps
100
includes capacitors
13
and
15
and transistors
14
and
16
. And, a feedback circuit for controlling a high voltage level is placed between the charge pumps
100
and an output terminal
19
.
The feedback circuit comprises an output voltage sense part
200
sensing a voltage of the output terminal
19
, a reference voltage generation part
300
generating a reference voltage
310
, a voltage comparison part
400
comparing the reference voltage
310
of the reference voltage generation part
300
to a sense voltage
260
of the sense part
200
, and a control signal generation part
500
generating control signals
17
and
18
for controlling operation of the charge pumps
100
in accordance with a comparison signal
410
of the voltage comparison part
400
.
The output voltage sense part
200
comprises resistors
201
and
202
connected in series between the output terminal and a ground Vss, a dynamic resistor part
250
including dynamic resistors
203
,
205
,
204
, and
206
connected to the resistor
210
in parallel, and EEPROM fuse circuits
210
and
220
deciding a resistance of the dynamic resistor part
250
by sensing a programming state of a flash cell.
The EEPROM fuse circuits
210
and
220
respectively include depletion transistors
211
and
221
of which drains are connected to a terminal of the power source voltage Vcc and of which gates and sources are connected to each other in common, flash cells
212
and
222
connected between the sources of the depletion transistors
211
and
221
and the ground Vss, respectively, and inverters
213
and
223
inverting a voltage at an output node. In this case, the flash cells
212
and
222
are constructed with floating-gate FET.
The reference voltage generation part
300
comprises an inverter
301
inverting a write enable signal /WE and a plurality of transistors
302
to
305
connected in series between the terminal of the power source voltage Vcc and ground Vss. In this case, the transistors
302
and
305
are depletion transistors and transistors
303
and
304
are NMOS transistors. Moreover, gates of the depletion transistors
302
and
305
are grounded, while gates of the NMOS transistors
303
and
304
are connected to an output terminal of inverter
301
.
The voltage comparison part
400
comprises a differential amplifier amplifying differentially the sense voltage
260
of the output voltage sense part
200
and the reference voltage
310
of the reference voltage generation part
300
by being enabled by an output of the inverter
406
and inverters
407
to
409
outputting a comparison signal
410
by inverting an output of the differential amplifier successively.
The control signal generation part
500
comprises NOR gates
501
and
502
NORing an output signal of the voltage comparison part
400
, the write enable signal WE, and a clock signal &PHgr;
p
and inverters
503
to
505
outputting control signals
17
and
18
by inverting outputs of the NOR gates
501
and
502
, respectively.
Operation of the above-constructed high voltage generation circuit according to the related art is explained by referring to the attached drawing as follows.
First, for an initial stage during which the charge pumps does not carry out pumping operation, a voltage level of the output terminal
19
maintains Vcc−Vth by the pull-up transistor
12
.
When the write enable signal /WE is shifted to a low level on a data program stage, the reference voltage generation part
300
outputs the predetermined reference voltage
310
divided by the depletion transistors
302
and
305
, and the voltage comparison part
400
outputs the comparison signal
410
by comparing the reference voltage
310
to the sense voltage
260
of the output voltage sense part
200
which is determined by the resistor distribution.
Namely, as the reference voltage
310
is higher than the sense voltage
260
at the present stage, the differential amplifier outputs an output signal of high level, and the comparison signal
410
becomes a low level since the output signal of high level is inverted successively by the inverters
407
and
409
.
Therefore, the control signal generation part
500
becomes enabled by the write enable signal /WE, and then responds to the input clock signal &PHgr;
p
when the comparison signal
410
is on low level. Thus, the control signal generation part
500
generates pump control signals
17
and
18
having different levels. And, the charge pumps
100
initiate pumping operation in accordance with the pump control signals
17
and
18
.
Operation of the charge pumps
100
is explained in detail as follows.
First of all, the drain of the NMOS transistor
14
is pre-charged with a voltage Vcc−Vth supplied through the other NMOS transistor
11
on the initial stage. In this case, the pump control signal
17
inputted to the capacitor
13
maintains a low level Vss.
When the pump signal
17
is shifted to a high level Vcc on the data program stage, a drain voltage of the drain of the NMOS transistor
11
increases to 2Vcc−Vt by the pumping operation of the capacitor
13
and the other NMOS transistor
14
is turned on, simultaneously. Therefore, the drain voltage 2Vcc−Vt of the NMOS transistor
11
is reduced to the extent of a threshold voltage Vt and then transferred to the drain of the NMOS transistor
16
, whereby the drain of the next NMOS transistor
16
becomes pre-charged with 2(Vcc−Vt). In this case, the other pump control signal
18
inputted to the capacitor
15
maintains the low level Vss.
Thereafter, when the pump signal
18
is shifted to a high level, the drain voltage of the NMOS transistor
16
is increased to 3Vcc−2Vt by pumping operation of the capacitor
15
and the NMOS transistor
16
becomes turned on. The drain voltage 3Vcc−2Vt of the NMOS transistor
16
is reduced to the extent of the threshold voltage Vt and then transferred to the drain of the NMOS transistor
14
of the next charge pump
100
. Therefore, a drain of the NMOS transistor
14
of the next charge pump
100
is pre-charged with 3(Vcc−Vt).
Thus, a plurality of the charge pumps
100
carry out the pre-charging and pumping operation repeatedly in accordance with the pump control signals
17
and
18
, thereby increasing the voltage level of the output terminal step by step.
While a plurality of the charge pumps
100
increase the voltage of the output terminal
19
, the output voltage sense part
200
plays a role of determining a level of the output voltage
207
to sense the voltage of the output terminal
19
. Namely, the NMOS transistors
205
and
206
become turned on/off by changing information of the flash cells
212
and
222
in accordance with levels of control signals
251
to
254
, whereby the resistors
203
and
204
are enabled to function as substantial resistance values.
Thereafter, when the sense voltage
260
becomes higher than the reference voltage as the voltage of the output terminal
19
is increased by the pumping operation of the charge pumps
100
, the voltage comparison part
400
outputs the comparison signal
410
of high level. Therefore, the control signal generation part
500
becomes disabled by the comparison signal
410
of high level, whereby the charge pumps
100
stop the pumping operation.
Unfortunately,
Hynix / Semiconductor Inc.
Tra Quan
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