Semiconductor integrated circuit

Details Semiconductor integrated circuit Semiconductor integrated circuit

2003-12-30

2004-10-19

Zarneke, David A. (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S763010

Reexamination Certificate

active

06806726

ABSTRACT:

TECHNICAL FIELD
The present invention relates to the technology of semiconductor integrated circuits, and, more particularly, to a technique which can be applied effectively to the measurement of leakage current in a semiconductor integrated circuit, and, even more particularly, to a technique which is useful for the measurement of leakage current of a CMOS integrated circuit.
BACKGROUND OF THE INVENTION
For the detection of short-circuiting or breakdown of the pn junction of a semiconductor integrated circuit and the detection of breakdown of the gate insulation film of a MOSFET, a leakage current which is caused by these events is measured . A CMOS circuit has no or a very small load current in its inactive state, and, accordingly, the presence or absence of a leakage current can be determined by applying a voltage thereto and measuring the load current.
However, due to the trend toward higher circuit integration, a lower threshold signal level and a higher chip temperature resulting from a lower operating voltage, the load current of a MOSFET in the inactive state has increased, making it difficult to discriminate a leakage current, and, consequently it has become difficult to measure the leakage current accurately in the conventional manner based on voltage application and load current measurement.
Japanese Patent Unexamined Publication No. Hei 9(1997) - 101347 describes a technique which resembles and precedes the present invention.
FIG. 11
of the accompanying drawings shows a representative example of the above-referenced technique, which is intended to find a circuit having a leakage current based on the following circuit arrangement. The internal circuit is segmented into multiple blocks, and the blocks (inner circuits a
1
-a
5
) are provided on their power voltage V
DD
side with switching MOSFETs S
1
-S
5
which can be turned on or off selectively in response to control signals received on the external terminals (pads) P
1
-P
5
. The blocks (inner circuits a
1
-a
5
) are further provided on their ground voltage GND side with a leakage current lead-out circuit
21
, which is formed of a transistor
27
and a current mirror circuit (
29
,
31
), for shutting off the load current of the inner circuits upon detection of a leakage current. The circuit arrangement includes a leakage current detecting circuit which is formed of a reference current generation circuit
17
connected in series to one transistor of the current mirror circuit and an inverter
19
which is adapted to compare the leakage current flowing through the leakage current lead-out circuit
21
with the reference current provided by the reference current generation circuit
17
.
Although this technique is capable of finding a circuit having a leakage current, this “tandem circuit arrangement” having the MOS transistors connected on the power voltage V
DD
side and ground voltage GND side makes the supply voltage of the inner circuits lower than the power supply voltage on the chip terminal. On the other hand, a power supply voltage at a certain voltage level or higher is needed for the normal operation of the inner circuits. For this reason, the circuit arrangement cannot be fully adaptive to the trend toward provision of a lower power voltage for the semiconductor integrated circuits. Moreover, if the reference current generation circuit
17
or inverter
19
used in the leakage current lead-out circuit and leakage current detecting circuit fails, a leakage current cannot be detected or will be detected erroneously.
Although the above-referenced technique also is applicable to an embodiment (
FIG. 11
of the above-mentioned patent publication) including a leakage current detecting circuit for each segmented inner circuit, a leakage current detecting circuit having two MOS transistors in tandem connection (
FIG. 12
of the above-mentioned patent publication) cannot be fully adaptive to the trend toward provision of a lower power supply voltage for the semiconductor integrated circuits.
It is an object of the present invention to provide a technique for the testing of semiconductor integrated circuit which capable of detecting easily and accurately the presence or absence of a leakage current in excess of a specified amount in a CMOS integrated circuit chip.
Another object of the present invention is to provide a technique for a semiconductor integrated circuit which is capable of detecting a leakage current even in the case of a low-voltage design.
Still another object of the present invention is to provide a technique for a semiconductor integrated circuit which is capable of detecting an abnormality in a leakage current detecting circuit.
These and other objects and novel features of the present invention will become apparent from -the following description taken in conjunction with the accompanying drawings.
SUMMARY OF THE INVENTION
Among the aspects of the present invention disclosed in this specification, representative features are summarized as follows.
A semiconductor integrated circuit is segmented into multiple blocks, and each block comprises a plurality of CMOS circuits connected between one (e.g., ground point) of at least two potential points (power voltage V
DD
and ground potential) and a respective switching transistor, which can be controlled by a test mode control signal to shut off the current flowing through each CMOS circuit; each block is and also provided with a leakage current detecting circuit, with a signal resulting from the logical sum of the outputs of all leakage current detecting circuits of the multiple blocks being led out of the semiconductor integrated circuit through an external output terminal common to all blocks. The leakage current detecting circuit is arranged so that it can implement the detection of an abnormality in the leakage current detecting circuit itself (self check) and the output of the detection result.
The leakage current detecting circuit with the ability of self check is conceivably a combined circuit including a switching circuit which can connect the circuit in the block to a common constant current source, a potential detecting circuit which is formed of an inverter and the like and designed to detect the potential of an arbitrary node on the current path of the constant current source and have its output varied in response to a leakage current larger than a certain value, a means of supplying a pseudo leakage current to the constant current source, and a current path switching means which is connected to the output terminal of the potential detecting circuit and is adapted to switch between the pulling and pushing of a current from/to the output terminal depending on the control mode.
The above-mentioned means can detect easily and accurately whether or not a leakage current more than a specified amount is flowing through the CMOS integrated circuit by merely checking a specific external output terminal. Based on the design which calls for leading out the signal resulting from the logical sum of the outputs of leakage current detecting circuits of all blocks through the common external output terminal, the increase in the number of external terminals can be minimized.
Based on the provision of the switching transistor connected between the CMOS circuit of each block and one potential point (e.g., ground point) so as to shut off the current flowing through the CMOS circuit under control of the test mode control signal, the number of transistors in tandem connection in each block can be reduced, which is advantageous to the trend toward use of a lower power supply voltage for semiconductor integrated circuits.
In an alternative design, instead of leading out the signal resulting from the logical sum of the outputs of all leakage current detecting circuits through the common external output terminal, a selector circuit is provided between the output terminals all leakage current detecting circuits and the common external output terminal so that the detection signal of each leakage current detecting circuit is led out selectively. This arrangement

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