Circuit for generating data strobe signal of semiconductor...

Details Circuit for generating data strobe signal of semiconductor... Circuit for generating data strobe signal of semiconductor...

2007-06-12

2007-06-12

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Signals

C365S233100

Reexamination Certificate

active

11606928

ABSTRACT:
A circuit for generating a data strobe signal of a semiconductor memory device comprises a plurality of internal clock delay units, a selecting control unit and a pulse generating unit. The plurality of internal clock delay units delay an internal clock signal in response to a plurality of CAS latency signal. The selecting control unit logically combines a data latch control signal to latch input data with output signals from the plurality of internal clock delay units. The pulse generating unit generates the data strobe signal having a predetermined pulse in response to an output signal from the selecting control unit. In the circuit, a tDQSS margin is regulated depending on change of tCK of an operating frequency in response to a CAS latency signal.

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patent: 2004-145999 (2004-05-01), None
patent: 2004-192791 (2004-07-01), None
patent: 2004-327008 (2004-11-01), None

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