Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate
2007-01-09
2007-01-09
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Signals
C365S233100
Reexamination Certificate
active
11115351
ABSTRACT:
A circuit for generating a data strobe signal of a semiconductor memory device comprises a plurality of internal clock delay units, a selecting control unit and a pulse generating unit. The plurality of internal clock delay units delay an internal clock signal in response to a plurality of CAS latency signal. The selecting control unit logically combines a data latch control signal to latch input data with output signals from the plurality of internal clock delay units. The pulse generating unit generates the data strobe signal having a predetermined pulse in response to an output signal from the selecting control unit. In the circuit, a tDQSS margin is regulated depending on change of tCK of an operating frequency in response to a CAS latency signal.
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patent: 6552957 (2003-04-01), Yagishita
patent: 6636446 (2003-10-01), Lee et al.
patent: 6760261 (2004-07-01), Partsch et al.
patent: 2003/0182595 (2003-09-01), Carnevale et al.
patent: 2004-145999 (2004-05-01), None
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Cho Ho Youb
Ha Sung Joo
Heller Ehrman LLP
Hynix / Semiconductor Inc.
Le Vu A.
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