Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
1999-04-22
2001-02-27
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S159000, C331S00100A, C331S017000, C331S040000, C331S041000
Reexamination Certificate
active
06194931
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a backbias voltage (VBB) generation circuit and a method of generating backbias voltage corresponding to the high frequency in a semiconductor memory device.
2. Description of the Related Art
In a semiconductor memory device, a backbias voltage is a voltage lower than an external minimum voltage and is used for the following benefits:
First, the backbias voltage VBB prevents a PN junction in a memory chip from being forward-biased, which would cause a loss of data in memory cells or latch-up phenomena. Even if the data signal applied to an input terminal does not meet the desired level, a PN diode does not turn on when a backbias voltage is applied. Thus, electrons of the input terminal are not injected into the P-well.
Second, the circuit operation is stabilized by reducing the threshold voltage fluctuation of a MOS transistor caused by the body effect. If a backbias voltage VBB is applied, the threshold voltage is less affected by the source potential change. Thus, a backbias voltage VBB reduces the variation in the threshold voltage and, in turn, can reduce the voltage applied to the wordline, which increases the reliability of a device.
Third, the backbias voltage VBB increases a threshold voltage of a parasitic MOS transistor. The increased threshold voltage of the parasitic MOS transistor reduces the concentration of a channel stop impurity under a field oxide layer, which reduces the possibility of junction breakdown and current leakage.
Fourth, the backbias voltage VBB reduces PN junction capacitance formed between an N
+
region (drain and source) of an NMOS and P-well, so that the semiconductor memory device circuit can operate at a higher speed. The reduction in the PN junction capacitance reduces the parasitic capacitance of bit line contact and increases the data flow transmitted to the bit line.
One type of backbias voltage generation circuit is disclosed in U.S. Pat. No. 5,157,278. The backbias voltage generation circuit of the U.S. Pat. No. 5,157,278, as shown in
FIG. 1
, detects a backbias voltage and then drives a self-oscillating circuit to thereby generate the backbias voltage. One pumping circuit operates regardless of whether the device is in a standby mode (in which a memory neither reads nor writes) or in an active mode (in which the memory reads or writes).
However, the backbias voltage generation circuit disclosed in U.S. Pat. No. 5,157,278 does not sufficiently compensate for a semiconductor device's substrate current generated while in an active mode. Instead, the backbias voltage generation circuit disclosed in the U.S. Pat. No. 5,157,278 employs a small capacity pump driver in order to minimize the current consumption in a standby mode.
A similar backbias voltage generation circuit disclosed in U.S. Pat. No. 4,455,628 and shown in
FIG. 2
, drives a pump driver by a self-oscillating circuit operating without a backbias voltage detecting circuit. The pump is driven when a row address strobe signal (/RAS) and a column address strobe signal (/CAS) are activated.
The prior art backbias voltage generation circuits disclosed in both U.S. Pat. Nos. 5,157,278 and 4,455,628 also enables the self-oscillating circuit and drives the pump driver by detecting the backbias voltage or the activation of /RAS and /CAS, which causes the pumping operation to last longer than the active period of each row. Thus, the pump driver does not have sufficient temporal margins between one pumping operation and the next pumping operation, which increases the backbias voltage fluctuation.
SUMMARY OF THE INVENTION
It is an objective of the present invention to provide a backbias voltage generation circuit and a method for reducing the backbias voltage fluctuation depending on the operational frequency of a semiconductor memory device.
Accordingly, to achieve the above objective of the present invention, there is provided a backbias voltage generator for a semiconductor memory device, comprising, at least one normal driving unit that pumps down the backbias voltage independent of the chip control signal indicating the activation of the semiconductor memory device, an active driving unit that pumps down the backbias voltage more greatly than the normal driving unit while the chip control signal is active, in response to the chip control signal, when the active control signal is detected, and a level detecting unit that generates a normal control signal and an active control signal activated when the backbias voltage is higher than the predetermined level. The active driving unit includes a counter that generates signals to enable at least two pump drivers alternately in response to the activating edge of said chip control signal.
Preferably, the active driving unit comprises, a counter circuit for providing first edge detecting signal and second edge detecting signal which transits its level alternately in response to the activating edge of the chip control signal, and an active pumping unit that pumps down the backbias voltage, when the first or second edge detecting signal is activated.
To achieve the above objective of the present invention, there is provided a method for generating a backbias voltage for a semiconductor memory device, having a normal driving unit that operates independent of a chip control signal indicating an activation of the semiconductor memory device and an active driving unit that operates in response to a chip control signal, comprising the steps of: (a) determining whether the backbias voltage is equal to or higher than the predetermined level; (b) determining whether the semiconductor memory device is activated or not; (c) driving the normal driving unit to pump down the backbias voltage when the backbias voltage is equal to or higher than the target level in step (a); and (d) driving the active driving unit to pump down the backbias voltage in response to the activation edge of a row activation signal indicating the activation of the semiconductor memory device in step (b), when the backbias voltage is equal to or higher than the target level in step (a).
According to the circuit and method of the present invention, the semiconductor memory device pumps down the backbias voltage corresponding to every activating edge of the chip control signal to thereby minimize the backbias voltage variation in an active mode.
REFERENCES:
patent: 4322643 (1982-03-01), Preslar
patent: 4455628 (1984-06-01), Ozaki et al.
patent: 5157278 (1992-10-01), Min et al.
patent: 5534821 (1996-07-01), Akiyama et al.
patent: 5740213 (1998-04-01), Dreyer
patent: 5821789 (1998-10-01), Lee
patent: 5870003 (1999-02-01), Boerster
Callahan Timothy P.
Howrey Simon Arnold & White , LLP
Liu An T.
Samsung Electronics Co,. Ltd.
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