Circuit for generating an internal clock for data output buffers

Details Circuit for generating an internal clock for data output buffers Circuit for generating an internal clock for data output buffers

1996-12-20

1998-12-01

Tran, Toan

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

327293, 327299, 327 99, H03K 2100

Patent

active

058444386

ABSTRACT:
An internal clock generating circuit for data output buffers of a synchronous DRAM device, which produces an internal clock with reference to either the positive edge or the negative edge of the system clock CLK by comparing the reference time t.sub.CLref(OH) for insuring a low level time tCL of the system clock CLK and output hold time t.sub.OH, and which can sufficiently insure the data output setup time t.sub.OS and data output hold time t.sub.OH regardless of the frequency of the system clock by making the generation points of the internal clock to be varied depending on the frequency of the system clock.

REFERENCES:
patent: 4748417 (1988-05-01), Spengler
patent: 5136180 (1992-08-01), Caviasca et al.
patent: 5243637 (1993-09-01), Flaherty et al.
patent: 5483185 (1996-01-01), Scriber et al.

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