Circuit for generating almost full and almost empty flags in res

Details Circuit for generating almost full and almost empty flags in res Circuit for generating almost full and almost empty flags in res

1998-11-30

2000-05-30

Lee, Thomas C.

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output data buffering

710 52, 36518907, 365236, G06F 1314

Patent

active

060702036

ABSTRACT:
An efficient design to generate a programmable almost empty or programmable almost full flags. The present invention accomplishes this by efficiently evaluating the read count minus write count plus a user programmed offset being greater than or equal to zero for the programmable almost empty flag generation. Similarly, evaluating write count minus the read count plus the user programmed offset minus the size of the FIFO is greater than or equal to zero for the programmable almost full flag generation. The counters in the FIFO count from 0 to twice the size of the FIFO minus one and the user programmed offset can be between 0 to the size of the FIFO minus one. The offset has one less bit than the read and write counters. The processing block masks out the higher order bits of the Offset input based on the size of the FIFO. The first stage performs the bit wise addition of the offset, read counter and write counter inputs without any carry chain propagation. From the sum and carry outputs of the first stage bitwise addition, bits with equal weights are united and the overall carry out of this addition is generated very efficiency. The overall carry represents the external almost empty or almost full flag.

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