Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis
Reexamination Certificate
2000-12-19
2004-04-06
Lee, Thomas (Department: 2185)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Reexamination Certificate
active
06718478
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a circuit for generating a start pulse signal for a source driver integrated circuit (IC) in a thin film transistor-liquid crystal display (TFT-LCD) and in particular to an improved circuit for generating a start pulse signal for a source driver IC in a TFT-LCD which can remarkably reduce a layout area, and restrict setup and hold violations.
2. Description of the Background Art
In general, a TFT-LCD that is a kind of an active LCD is thin and light-weighted and consumes small power, and thus has been popularly used for a portable display device, such as a notebook computer. Nowadays, the TFT-LCD is even employed for the operation of vehicles and the audio/video of monitors.
A start pulse signal STH is a control signal inputted to a source driver IC through a timing controller in the AFT-LCD. The start pulse signal STH serves to inform that an effective input data is included in data inputted from a data driver to the source driver IC. A circuit for generating the start pulse signal STH generates the start pulse signal STH at an initial period of a data enable signal DE. The constitution and operation of a conventional circuit for generating the start pulse signal will now be described with reference to FIG.
1
.
FIG. 1
is a circuit diagram illustrating the conventional circuit for generating the start pulse signal, including: a 5 bit counting unit
10
for counting a main clock signal MCLK; an AND gate AND
1
for receiving a data enable signal DE and a reset signal Reset; a latch unit
20
consisting of first to fifth flip-flops
21
~
25
for respectively receiving the output signal from the 5 bit counting unit
10
as an input signal S, the main clock signal MCLK as a trigger input, and the output signal from the AND gate AND
1
as a reset signal R, and feedback-inputting an output signal D to the 5 bit counting unit
10
; a decoding unit
30
consisting of a NAND gate NA
1
for receiving a complementary signal of the output signal D from the first to fourth flip-flops
21
~
24
, and an AND gate AND
2
for receiving complementary signals of output signals from the NAND gate NA
1
and the fifth flip-flop
25
; and a sixth flip-flop
40
for receiving the output signal from the NAND gate NA
1
and a complementary signal of the output signal from the AND gate AND
2
as input signals S, S′, the reset signal Reset as a reset signal R, and the main clock signal MCLK as a trigger input T, and generating the start pulse signal STH.
When the reset signal Reset and the data enable signal DE are at a high level, the first to fifth flip-flops
21
~
25
of the latch unit
20
receive the main clock signal MCLK as the trigger input T and convert output signals in a clock leading edge. Here, the output signals D from the first to fifth flip-flops
21
~
25
are inputted to the decoding unit
30
, and at the same time feedback-inputted to the 5 bit counting unit
10
.
The decoding unit
30
combines the output signals from the first to fifth flip-flops
21
~
25
, and inputs it to the sixth flip-flop
40
for generating the start pulse signal STH.
The sixth flip-flop
40
receives the output signal from the NAND gate NA
1
and the complementary signal of the output signal from the AND gate AND
2
as input signals S and S′, the reset signal Reset as a reset signal R, and the main clock signal MCLK as a trigger input T, thereby generating the start pulse signal STH.
However, as illustrated in
FIG. 1
, the conventional circuit for generating the start pulse signal includes the 5 bit counting unit
10
for receiving and counting the main clock signal MCLK, the latch unit
20
consisting of 5 flip-flops for latching the output from the counting unit
10
, the decoding unit
30
for decoding the output signal from the latch unit
20
, and the flip-flop for generating the start pulse signal by synchronizing the output signal from the decoding unit
30
to the main clock signal MCLK. As described above, the conventional circuit for generating the start pulse signal requires many devices, which results in increase of a chip area. In addition, the setup and hold violations are generated.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to provide a circuit for generating a start pulse signal for a source driver IC in a TFT-LCD which can remarkably reduce a layout area and restrict setup and hold violations, by generating the start pulse signal by a simple circuit for detecting a leading edge of a data enable signal, instead of a complicated counter circuit.
In order to achieve the above-described object of the present invention, there is provided a circuit for generating a start pulse signal for a source driver IC in a TFT-LCD, including: a first latch unit for receiving a data enable signal and a reset signal, extracting a leading edge of the data enable signal in a leading edge of a main clock signal, and latching the data enable signal in a trailing edge thereof; a logic gate unit for receiving a complementary signal of the output signal from the first latch unit and the data enable signal, and generating a pulse signal in a leading edge of the data enable signal; and a second latch unit for receiving the output signal from the logic gate unit and the reset signal, outputting the output signal from the logic gate unit as a start pulse signal in the leading edge of the main clock signal, and latching the output signal from the logic gate unit in the trailing edge thereof.
In accordance with a preferred aspect of the present invention, the first latch unit is an RS flip-flop.
In accordance with another preferred aspect of the present invention, the logic gate unit is an AND gate.
In accordance with still another preferred aspect of the present invention, the second latch unit is a D flip-flop.
REFERENCES:
patent: 5565812 (1996-10-01), Soenen
patent: 5592113 (1997-01-01), Quiet et al.
patent: 6636980 (2003-10-01), Gervais et al.
Jeong Jin Young
Kim Yong Il
Yoon Sang Ho
Boe-Hydis Technology Co., Ltd.
Chandrasekhar Pranav
Lee Thomas
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