Circuit for generating a spread spectrum clock

Details Circuit for generating a spread spectrum clock Circuit for generating a spread spectrum clock

1995-11-28

1997-03-11

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

331 18, 331 25, 327156, 327157, H03D 324

Patent

active

056109555

ABSTRACT:
A phase-locked loop (PLL) circuit which receives a signal at a reference frequency to generate a spread spectrum clock signal. A first divider circuit in the PLL and connected to the PLL input terminal generates an output signal at the reference frequency divided by a first variable integer M. A second divider circuit connected to the PLL output terminal generating an output signal at the output frequency divided by a second variable integer N. The PLL also has a circuit which periodically varies the first variable integer M and the second variable integer N. This permits the frequency of the output signal to vary precisely between two predetermined frequencies to spread the spectrum of output frequencies.

REFERENCES:
patent: 3815042 (1974-06-01), Maunsell et al.
patent: 4574243 (1986-03-01), Levine
patent: 5113152 (1992-05-01), Norimatsu
patent: 5162746 (1992-11-01), Ghoshal
Hardin et al., "Spread Spectrum Clock Generation for the Reduction of Radiated Emissions", IEEE, 7803-1398-4/94, pp. 227-231.
International Microcircuits Inc., "CMOS LSI, Reduced EMI Clock Generator", May 2, 1994, pp. 1-8.
International Microcircuits Inc., "CMOS LSI, Spread Spectrum Clock Generator", Apr. 20, 1994, pp. 1-3.
International Microcircuits Inc., "CMOS LSI Spectrum Spread Clock Generator", Apr. 21, 1995, pp. 1-7.

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