Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
2000-03-10
2001-05-15
Ghebretinsae, Temesghen (Department: 2631)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C375S376000, C327S147000
Reexamination Certificate
active
06233296
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a circuit for generating a signal with adjustable frequency. In particular, the invention is intended for generating a radiofrequency signal, as is required for example in radio transmission apparatuses, cordless telephones, mobile telephones and other transmission apparatuses and systems. The possibility, afforded by the invention, of adjusting the frequency of the generated signal can be used for example for the purpose of frequency and/or phase modulation of the generated signal. Furthermore, the generated signal may serve as an (unmodulated) carrier signal whose frequency is kept stable with the aim of automatic frequency control independently of changing operating conditions (supply voltage, temperature, etc.).
It has been known heretofore to generate a signal with adjustable frequency by means of a digital synthesis circuit. Such a circuit, which is also referred to as a DDS circuit (DDS=direct digital synthesizing), is contained for example in the module with the type designation AD7008 available from Analog Devices.
That digital synthesis circuit has an accumulator, that is to say a clocked, storing summer with feedback whose counting range is swept through cyclically. The cycle duration depends on the clock frequency and on the magnitude of an applied additive value. The respective present counter reading of the accumulator is output to a look-up table, in order to generate data values which form a sine curve from the counting range that is swept through in sawtooth fashion. The data values generated by the look-up table are converted into an analog, sinusoidal output signal of the digital synthesis circuit by a digital/analog converter.
The output signal of a digital synthesis circuit of this type has relatively poor spectral purity, however. This is due to the fact that the resolution of the digital/analog converter is limited. Furthermore, the look-up table and the digital/analog converter require a high outlay on components, which is higher, the more stringent the requirements made of the signal quality. Finally, the digital/analog converter, in particular, has a relatively high current consumption and is poorly integrable, which is disadvantageous for use in battery-operated apparatuses, such as mobile telephones, for example.
U.S. Pat. No. 5,517,534 discloses, a PLL circuit, i.e., a circuit for generating a signal with adjustable frequency, with the following features: a reference oscillator generates a reference signal. A comparison signal device having an addition value input and a clock input generates a digital comparison signal, whose frequency depends on an addition value signal present at the addition value input and on a clock signal present at the clock input. A phase comparator generates a tuning signal depending on the result of a comparison of the phase of the reference signal with the phase of the comparison signal. An oscillator is driven by the tuning signal and generates the output signal and an oscillator signal, from which the clock signal present at the clock input of the comparison signal device can be derived. The comparison signal device has an accumulator clocked by the clock signal, and the comparison signal is derived from the counter reading of the accumulator. In other words, the pulse generator is clocked by the output signal of the PLL circuit (oscillator signal) and is enabled or inhibited depending on counter readings of a plurality of accumulators.
It has become known from the article “A Short Survey of Frequency Synthesizer Techniques” by V. Reinhardt et al. in Proceedings of the 40th Annual Frequency Control Symposium, Philadelphia, 1986, pages 355-65, to add a random number to the output signal of an accumulator in order to reduce the intensity of sidebands in the output spectrum of DDS circuits.
Additional information, in this context, may be gleaned from the German published patent application DE 196 53 022 A1 (not prior art). There is shown a frequency synthesizer in which overflow pulses of a digital accumulator are fed to a phase detector of a phase locked loop.
SUMMARY OF THE INVENTION
The object of the invention is to provide a circuit for generating a signal with adjustable frequency which overcomes the above-noted deficiencies and disadvantages of the prior art devices and methods of this kind, and which generates a high-quality output signal, has a low current consumption and outlay on components and is readily integrable. It is a particular object to shift low-frequency interfering frequency components in a tuning signal, which can occur in the event of unfavorable operating states, into a higher frequency range by means of the invention.
With the above and other objects in view there is provided, in accordance with the invention, a circuit for generating a signal with adjustable frequency, comprising:
a reference oscillator for generating a reference signal;
a comparison signal device having an addition value input receiving an addition value signal and a clock input receiving a clock signal, the comparison signal device generating a digital comparison signal with a frequency dependent on the addition value signal present at the addition value input and on the clock signal present at the clock input;
a phase comparator connected to receive the reference signal from the reference oscillator and the comparison signal from the comparison signal device, the phase comparator comparing a phase of the reference signal with a phase of the comparison signal and generating a tuning signal in dependence on a result of the comparison;
an oscillator connected to the phase comparator and driven by the tuning signal, the oscillator generating an output signal of the circuit and an oscillator signal defining the clock signal present at the clock input of the comparison signal device; and
the comparison signal device having an accumulator clocked by the clock signal and having a counter reading;
wherein the comparison signal is derived from the counter reading of the accumulator, and instants of state changes in the digital comparison signal are subjected to jittering by comparison with clock instants of the clock signal.
The invention is based on the fundamental idea of using a controlled oscillator for generating the output signal. The oscillator is tracked in a control loop similar to a PLL (phase locked loop). In this case, the invention makes use of the insight that, instead of a complex digital synthesis circuit, a very much simpler comparison signal device which generates a digital comparison signal from an addition value signal and a clock signal can be used in a control loop of this type.
The circuit according to the invention has a high output signal quality, because the output signal is generated by the controlled oscillator with high spectral purity and an accurately controlled frequency. Despite this high quality, only a relatively low outlay on components is necessary, and the circuit is readily integrable owing to the high digital proportion. In particular, a digital/analog converter is not required, because the comparison signal is a digital signal.
The term “digital signal” as it is used in this text should be understood to be any signal or signal burst from which digital values can be derived. In particular, a digital signal may therefore have a plurality of partial signals which are transmitted on a respective line of a parallel data transmission path. Each partial signal then defines a bit from a digital data word at each instant.
The digital comparison signal is preferably a binary signal having a width of one bit. Such a signal suffices for communicating the required frequency information. The circuit is then particularly simple.
An accumulator as it is used in the novel circuit can be easily integrated as a fully digital component. In a preferred manner, no analog components such as digital/analog converters are provided.
In accordance with an added feature of the invention, the accumulator has a most significant bit and an ove
Ghebretinsae Temesghen
Greenberg Laurence A.
Lerner Herbert L.
Siemens Aktiengesellschaft
Stemer Werner H.
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